High-voltage transient spikes generated during power conversion or gate-drive switching can be very harmful. In a motor-drive application, voltage derivation over time (dV/dt) transients may break the winding insulation, reducing motor life and impacting system reliability.
In circuits that use silicon MOSFETs and IGBTs as well as SiC MOSFETS, the usual way to reduce the transient response is to increase the value of the external gate resistor. Such devices typically have a high reverse transfer capacitance (Crss) or gate-drain Miller capacitance (Cgd). Increasing the gate resistance (Rg) is particularly effective at reducing dV/dt for fast switching applications.
An example use case is a totem-pole power factor correction (PFC), where lower switching losses result from a high dV/dt. However, with slower applications, such as a motor, the resistance value required to achieve a dV/dt within an acceptable range of say 5 to 8V/ns would be in the kilo-ohm range. A high Rg would lengthen the switch-on and -off delay considerably.
This article highlights three methods commonly employed for bringing dV/dt from 45V/ns down to 5V/ns, but without incurring excessive turn-on/turn-off delay times. To cover all options, we investigate using external gate-drain capacitor and RC snubber on the device and using a JFET direct drive approach.
In each case, a 1200V SiC FET in a T0247-4L package is used with an Rds(on) of 9 milli-ohm switching at 75 A/800V. Each of the scenarios explored is first simulated using a SPICE model of the SiC field-effect transistor (FET). The double-pulse circuit experiments measure turn-on and turn-off times to verify the simulation results.
Using an external Cgd capacitor
In this method, an external Cgd capacitor, Cgdext, is placed between the gate and drain of both the high- and low-side FETs of a half-bridge configuration (Figure 1).
Figure 1 This method uses a gate drive with an external Cgd for dV/dt control. Source: UnitedSiC
For the SiC FET, the Cgdext value is calculated to be 68 pF, and for simulation purposes, a series parasitic inductance (Lpar) of 20 nH is included. The parasitic inductance could be less in real situations using discretes and with the Cgd capacitors connected as close as possible to the FETs. If FET modules are used, the capacitor would need to be placed external to the module, representing closer to 20 nH parasitic inductance.
The results of the SPICE simulation and the experiment for the external Cgd capacitor are illustrated in Figure 2. Because Ids is relatively low during switching, estimated to be 0.54 A, the external capacitor can tolerate the 20 nH parasitic inductance. The dV/dt for this method is measured and calculated to be in the range 25 to 5V/ns when using the 68-pF capacitor and an Rg in the range of 10 to 33 Ω (Figure 3).
The results indicated that this method of reducing dV/dt is appropriate when using FET modules, placing Cgd on the PCB, and accepting a degree of parasitic inductance.
Using RC snubber on FETs
Another way of controlling dV/dt is by connecting an RC snubber circuit across the drain and source of the high-side and low-side FETs (Figure 4).
For this example, like the external gate-drain capacitor, a 20 nH parasitic inductance is added in series with the capacitor (Csnubber) and resistor (Rsnubber). When using discrete FETs, the RC components can be placed as closely as possible to the FETs, ideally connected directly to the leads, in which case the parasitic inductance would be minimal. The experimental snubber circuit used a 5.6 nF capacitor and a 0.5 Ω resistor. SPICE simulation and the results from the experiment indicated that the dV/dt could be reduced from 50 to 5V/ns using this approach (Figure 5).
Switching losses resulting from the addition of the snubber circuit are minimal with lower capacitance values, amounting to approximately 2 W with a 10-kHz switching frequency. The relatively high value of simulated parasitic inductance, 20 nH, indicated that the RC snubber arrangement could be placed external to FET modules and reduce dV/dt by 90%.
JFET direct-drive method
The final method of reducing dV/dt is the use of a direct-drive junction gate (JFET) arrangement. In this circuit, the silicon MOS device is turned on once at start-up and then the JFET gate is switched between -15V and 0V. A pulse width modulation (PWM) gate drive signal is required along with an enable signal, but the normally-off operation is maintained. The high-side JFET gate applies -15V to keep it off during switching transients.
Again, measurements are conducted with an experimental setup and circuit simulation using a SPICE model (Figure 6). Since the SiC JFET has significant Crss(Cgd), a small Rg of 4.7 Ω is sufficient to slow down dV/dt to 5V/ns.
Pros and cons
Table 1 highlights the summary of SPICE simulated predictions of the three different methods of reducing the dV/dt in a 75 A/800V circuit. Of the three, the JFET direct-drive approach produced the lowest energy loss. That said, the direct drive requires a -15V drive signal along with an enable signal, adding to component count and circuit complexity.
The external Cgd capacitor and RC snubber methods have shown slightly higher switching losses but they don’t require access to the JFET gate. Both of these methods can be easily achieved on a PCB when using discrete FETs.
The standard FETs from UnitedSiC don’t provide access to the gate of the JFET, but a new dual-gate product packaged in a TO247-4L package is in development. This approach is also suitable for use with modules that have a JFET gate pin added. In all cases, a 20 nH parasitic inductance is factored into the SPICE simulations, the results proving that a degree of inductance does not impact the reduction of dV/dt.
The RC snubber method has highlighted that it can’t control turn-on and turn-off of dV/dt independently (Table 1). However, separate Rg(on) and Rg(off) resistors allow independent control for the Cgd and direct drive JFET methods.
Zhongda Li is senior staff R&D engineer at UnitedSiC.