Why Physical Verification Is Only Getting Tougher With Advanced Nodes


IC designers are all too familiar with the pressure of verification deadlines prior to manufacturing. Factors that can slow down that physical verification process include complex designs, overlapped wiring, and intricate metal layouts—not to mention the addition of billions of transistors.

 

While it is easier to go from hardware to EDA, verifying and validating the hardware itself can take much longer

While it is easier to go from hardware to EDA, verifying and validating the hardware itself can take much longer. Image used courtesy of ACM Digital Library
 

These setbacks are only compounded as technology moves into more advanced nodes. Recently, Synopsys, a leading developer of EDA tools, released an IC validator to address time spent during EDA workflows. The company has partnered with Samsung and Microsoft with a new approach: utilizing the cloud. This IC validator is said to offer cloud-based access to physical verification, increasing productivity and design closure time. 

When it comes to physical verification, what are the challenges of scaled-down nodes? And how else are electronic design automation (EDA) companies helping to streamline the process? 

 

Design Rule Checking (DRC) and Layout Versus Schematic (LVS)

First, it’s important to understand two important steps that occur during the verification process: design rule checking (DRC) and layout versus schematic (LVS). DRC verifies whether a specific design meets the constraints imposed by a layout before manufacturing a physical product. LVS checks whether the designed IC matches up with the original schematic. 

 

LVS

Depiction of layout versus schematic (LVS) works. Image used courtesy of Synopsys
 

In the past, following standard procedures in physical verification (namely, with processes like DRC and LVS) did not slow down project timelines. However, as the EDA industry encounters more advanced space, power, and performance requirements, traditional DRC and LVS may ultimately delay designers.

 

Electrical Effects on Nanometer-scale Technology 

In the nanometer era, IC complexity grows faster than die areas. This makes the process for physical verification extend past scheduled timelines since there is a larger layout to check. Even after reviewing a layout, a design may still experience post-verification, electrical side effects. 

These complications cause functionality issues that can include:

  • Reduced wire
  • Lower power supply
  • Smaller threshold voltage
  • Higher power consumption

A leading problem is behavioral delays, which include signal integrity (SI) and an IR (voltage) drop. The voltage drop is nearly inevitable: as feature size decreases, resistance increases. Most analysis tools will overlook these issues, which leads to irreversible chip-level functionality issues. 

With challenges and electrical effects awaiting each design, how are these instances handled? Designers often look to silicon design and verification solutions from leading developers for solutions.  

 

Synopsys’ IC Validator 

Synopsys has focused on a cloud-based solution to address design complexity in deep learning, autonomous automation, and mobility in 5G networks.

When discussing physical verification, Synopsys advises to “clean as you go,” (PDF) an approach that suggests designers should run DRC at each design stage to avoid potential failures that usually don’t appear until the design phase has been completed. The company says its IC validator allows faster DRC flows and provides feedback for debugging hundreds of cores, which can take designers multiple hours or days to go through. 

 

DRC checking

“Clean as you go” DRC checking. Image used courtesy of Synopsys (PDF)
 

Synopsys also says its IC validator is able to deliver smart memory-aware load scheduling on Samsung’s SAFE cloud design platform and Microsoft Azure. 

 

Cadence’s Physical Verification System

Cadence is another EDA company that recently showcased its Physical Verification System (PVS). According to the company, this system is able to improve distributed processing performance for advanced nodes. Cadence claims the PVS will improve the debugging process that leads up to advanced node design signoff. 

 

PVS interactive suite

Cadence says its PVS interactive suite will lead designers to a faster path to the final sign-off. Image used courtesy of Cadence
 

Industry-standard DRC runs require prepped data and can take layout designers days to verify each phase. Alternatively, Cadence’s PVS is equipped with real-time mode for the model to edit as the design complies to sign off.

Since electrical shorts are difficult to debug in conventional practices, Cadence’s PVS offers an interactive short locator tool that is initiated during the first DRC run to quickly detect power shorts.

 

Siemens’ Calibre nmDRC

Another option comes from Siemens, which aims to address time spent on advanced nodes with equation-based DRC to multi-patterning, machine learning, and EDA in the cloud. One of the major value claims of Siemens’ Calibre tool suite is that it can handle “any design, at any node, at any foundry.”

 

Calibre nmDRC tool

Key characteristics of the Calibre nmDRC tool. Image used courtesy of Siemens
 

Siemens’ Calibre nmDRC is said to help designers verify all nodes—not only the advanced ones—providing strong debugging and verification throughout this process. Siemens asserts its software suite can be implemented into any existing system, giving designers flexibility for node mitigation.

 


 

What holdups have you encountered with physical verification as nodes have become more advanced? Share your experiences in the comments below.



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