The MCU-memory tie-up aims to better serve AIoT designs


Microcontroller (MCU) suppliers are steadily increasing the memory content in their devices, but is that enough to support design needs at the intersection of artificial intelligence (AI) and IoT technologies? Ultra-low-power MCU vendor Ambiq Micro joining hands with memory companies Winbond and AP Memory shows a tilt toward system-level engineering solutions.

When Ambiq announced the Apollo4 MCU last year, it claimed 2 MB of MRAM and 1.8 MB of SRAM storage capacity for handling complex algorithms and neural networks. Maybe it’s enough for some IoT applications, however, IoT endpoints and wearable designs supporting high-resolution displays and complex AI datasets demand faster processing of graphics, data, and user interfaces.

Not surprisingly, therefore, Ambiq has partnered with memory chipmakers Winbond and AP Memory to create a richer experience for IoT endpoints and wearable devices. It’s pairing its Apollo4 MCU with Winbond’s HyperRAM memory technology to develop ultra-low-power system solutions.

chart comparing HyperRAM with other DRAM memory chipsFigure 1 HyperRAM’s comparison with other DRAM memory chips underscores the pin-count and power consumption advantages. Source: Winbond

Winbond’s HyperRAM memory provides a compact alternative to traditional pseudo-SRAM and features a hybrid sleep mode. That, in turn, leads to a 50% lower power consumption than the normal standby mode. It extends densities up to 256 MB and 512 MB, and its volume production is expected in 2022.

Pact with AP Memory

Earlier, in March 2021, Ambiq entered into another system-level CPU-memory collaboration when it joined hands with PSRAM maker AP Memory to enable a rich experience for battery-powered endpoints. AP Memory’s low pin count PSRAM—which the company likes to call IoT RAM for its network-friendly features—provides the additional memory needed to augment the user experiences for edge and IoT applications.

illustration of a brain with connected devices representing PSRAM IoT RAMFigure 2 PSRAM combines a relatively simple SRAM interface with DRAM memory cell technology. Source: AP Memory

The demand for memory capacity in IoT and wearable designs is growing to the point that memory content built into MCUs falls short of the need for more enhanced displays, AI/ML processing, and complex audio use cases. As noted by Dan Cermak, vice president of architecture and product planning at Ambiq, “The partnerships between MCU suppliers and memory chipmakers enable IoT developers to future-proof their designs while offering more memory with longer battery life.”

Ivan Hong, vice president and general manager of the IoT business unit at AP Memory, calls this tie-up between low-power MCUs and memory chips imperative for delivering richer experiences in battery-powered intelligent endpoints, especially, when the AI and IoT segments are converging to create what’s increasingly called AIoT.

The AI and IoT worlds have started to merge with AI’s movement from cloud to edge, leading to this fundamental design shift in which already complex SoCs like Apollo4 are pairing with memory chips to better serve AI algorithms while simplifying IoT designs.

Majeed Ahmad, Editor-in-Chief of EDN, has covered the electronics design industry for more than two decades.

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