Most electronic clocks, be they analog or digital, use a crystal oscillator (XO) based on a 32.768 kHz crystal for their reference. In fact, it is same crystal that’s commonly used as a real-time clock for many microcontroller systems. These crystals have a typical annual stability of ±3ppm .
While this is sufficient enough for most applications, it is far too imprecise for designers who work on applications that require a much higher degree of stability. These so-called “time nuts”  must rely on high-precision time sources, such as oven controlled crystal oscillators (OCXO)  which offer an annual stability of ±2*10-8, or a cesium standard  with an even higher typical stability of ±3*10-12.
Unfortunately, upgrading an existing application from a basic crystal clock to a high stability frequency reference is not a straightforward task. This is because these high-precision sources operate at a standard 10 MHz, which is not an integer factor of the standard XO’s 32.768 kHz operating frequency.
One solution is a clock generator IC like the SI5351. It consists of a phase locked loop which multiplies the input frequency up to between 600 and 900 MHz and then divides that down to generate the output frequency. This is over complicated and likely to degrade the source with unwanted phase noise. The alternative solution proposed here is based on fractional division.
XO-driven electronic clocks divide their 32.768 kHz reference frequency down to 1 Hz with 15 consecutive divide-by-2 counters; 215 = 32768. Provided there are 32,768 pulses within one second, when and how those pulses occur is unimportant as the divider chain will smooth any pulse position or duty cycle irregularity.
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A finite state machine which gates an input 10 MHz clock to only allow through the first 32,768 pulses could fulfill this purpose. That would result however, in a highly irregular clock consisting of 32,768 pulses at a rate of 10 MHz and then a gap of almost 997 milliseconds. This may be too irregular for systems expecting a consistent 32.768 kHz clock.
Instead, fractional division can be used to identify common factors of 10 MHz and 32.768 kHz, as shown by the following equation:
The above equation shows the required division is possible with six divide-by-2.5 and one divide-by-1.25 operations. A divide-by-2.5 function can be produced using a standard divide-by-five logic element, such as the one available in the 74HC390 dual decade counter. The 74HC390 consists of two independent divide-by-2 and two divide-by-5 counters. The divide-by-5 has the following truth table (Figure 1) where QC is the most significant bit (MSB) and QA the least significant bit (LSB):
Figure 1 Truth table of a divide-by-5 counter.
For everyone five input clock pulses, QA pulses twice, hence it performs an irregular divide-by-2.5. If exactly 50% duty cycle is required, more sophisticated architectures are possible . Division-by-1.25 is more complex, but possible with a simple finite state machine, as it is equivalent to producing four output pulses for every five input pulses. This is achieved by AND-ing the input clock with the NOT QC output of a divide-by-five element. The truth table is thus (Figure 2) where ↑ is a rising clock:
Figure 2 Truth table of a divide-by-1.25 counter, derived from a divide-by-5 function.
The complete divider schematic is shown in Figure 3. QG1 is a 10 MHz crystal oscillator module, which could be a high stability OCXO if required. It provides a TTL compatible clock to the first divide-by-2.5, IC1A. Input A is the clock input of the 74HC390’s divide-by-2. In this case, A is unused so it is tied low, while QA, its corresponding output is left floating. Input B and outputs QB, QC and QD form the divide-by-5 with QB the LSB output.
Figure 3 Schematic diagram for divider chain.
QB of IC1A produces a 4 MHz clock which is then further divided down to 1.6 MHz by IC1B. IC2 and IC3 divide this further with divide-by-2.5 stages to 40.96 kHz. IC5C from a 74HC00 quad dual input NAND gate inverts the QD output of IC4A. This is fed to a NAND gate where it AND-ed with the incoming clock to form the divide-by-1.25 resulting in a 32.768 kHz clock at its output—pin 8.
To verify the theory, the circuit was prototyped on a breadboard as shown in Figure 4.
Figure 4 Breadboard implementation of divider chain with frequency counter.
The 10 MHz reference (QG1) is the metal canned oscillator module on the left-hand side. The four 74HC390s are next to that, with the 74HC00 on the far right of the proto board. The display shown just below the prototype is a ICM7216D based frequency counter, used to display the circuit’s output frequency.
The frequency counter in Figure 4 was configured with a one second gate time, during which the irregular pulse train was be smoothed. It used the same 10 MHz crystal oscillator as the divider chain for its reference. As anticipated, its display shows that the average output frequency is the 32.768 kHz specified by the design.
The divider circuit’s output pulse train was also recorded on a Keysight DSO-X 1102G oscilloscope as shown in Figure 5. The average frequency was measured with the internal counter and shown to be 32.768 kHz too. Also note that the irregular nature of the pulse train is clearly visible on the oscilloscope’s display.
Figure 5 Measured pulse train at output.
These positive results show how, with a bit of ingenuity, 32.768 kHz can be derived from 10 MHz.
 Golledge GWX-1610 1610 Package 32.768kHz Watch Crystal.
 A Time Nuts website: http://www.leapsecond.com/
 Golledge HCD220 10 MHz OCXO.
 Lindon L. Lewis, “An Introduction to Frequency Standards”.
 Yongping Xia, “Divide by 2.5”, Electronics World + Wireless World, December 1991, pp. 1051.
Gavin is an electronic engineer with Toshiba in Bristol UK and lifelong hardware hacker. He works mainly in advanced power amplifiers and other aspects of radio frequency engineering. In his spare time, he is happiest noodling around with audio electronics and vintage test equipment in his spare bedroom lab.