Teledyne e2v Boosts Broadband ADC Performance with Spur Reduction IP



Teledyne e2v announced the immediate availability of EV12AQ600/5 models featuring an integrated license key providing direct access to the novel ADX4 post-processing algorithm developed at SP Devices within the Teledyne group of companies. The ADX4 spur reduction IP dynamically attenuates spurious frequency components resulting from gain, offset and phase mismatches between the four ADC cores. Time-interleaving is a trusted architectural approach to boost ADC sampling rates. However, avoiding resulting spectral artifacts with calibration is especially challenging beyond 10-bit resolutions and in broadband applications. 

Applied to the EV12AQ600/5, time-interleaving four cores quadruples the sample rate from 1.6 to 6.4 GS/s. The mismatched errors between the ADC cores reduce spurious free performance. ADX4 delivers a spurious free dynamic range (SFDR) boost of up to 10 dB. That boost is particularly noticeable in broadband applications, and as it requires no hardware design changes is available on demand. The ADX4 code module is simply programmed into the post-processing FPGA. A modification that can even be retrofitted in the field. 



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