Cadence has announced support for the new TSMC N6RF Design Reference Flow and process design kit (PDK) to help accelerate mobile, 5G, and wireless innovation. The N6RF is TSMC’s latest new advanced RF CMOS semiconductor technology designed to make 5G and WiFi 6/6E better. N6RF is an advanced RFCMOS technology, that enables customer products to deliver full 5G/Wi-Fi 6 & 6E performance while maximizing battery life by leveraging its superior RF capability and digital PPA benefit.
Through the ongoing collaboration between Cadence and TSMC, mutual customers are already designing with the Cadence solutions for TSMC’s latest N6RF CMOS semiconductor technology. The Cadence RFIC solutions support the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence. Optimized for TSMC’s N6RF process technology, the Cadence Virtuoso Schematic Editor, Virtuoso ADE Suite, and the integrated Spectre X Simulator and RF option are included in the RF Design Reference Flow.
Customers can benefit from several key features, which enable them to effectively manage corner simulations, perform statistical analyses and achieve design centering and circuit optimization. Additionally, the flows offer seamless integration between the Cadence EMX Planar 3D Solver and the Virtuoso Layout Suite EXL implementation environment, which enables designers to streamline EM modeling tasks and leverage automation to stitch S-parameter models into the golden design schematic for RF simulations automatically.
For post-layout analysis, the S-parameter models are layered into Cadence Quantus Extraction Solution results for high-fidelity RF signoff circuit and EM-IR simulations. Overall, the new Cadence RFIC full flow offers an efficient methodology that lets engineers achieve design goals performance, power efficiency, and reliability in a single, tightly integrated design environment.
“Through our ongoing collaboration with Cadence, we’re making it easier for customers to achieve their productivity goals using the jointly developed design flow and our advanced N6RF process technology, which offers significant performance and power efficiency boosts,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “With the availability of the new PDK, those creating next-generation mobile, 5G, and wireless designs can adapt our technologies quickly and accelerate the path to advanced-node innovation.”
“The comprehensive Cadence RFIC solutions cover all aspects of RF design from RF custom passive device generation and modeling to EM-IR analysis with self-heating. With this unified flow, customers can focus on innovative design, rather than spending time managing disparate, error-prone toolsets,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “By working closely with TSMC, our customers have access to the advanced capabilities included with TSMC’s N6RF process technology and the RF design reference flow, enabling them to achieve SoC design excellence and deliver competitive designs to market much more efficiently.”