Last week, Intel held its third annual two-day Innovation event, a resurrection of the previous Intel Developer Forums (a “few” of which I attended back in the old days). The day-one keynote, focusing on silicon, was delivered by CEO Pat Gelsinger:
while Greg Lavender, Intel’s chief technology officer, handled the day-two keynote duties, centering on software:
The big news coming out of the show was the public unveil of Intel’s chiplet-implemented Meteor Lake CPU architecture, now referred to as Core Ultra in its high-end configurations (the company is deprecating the longstanding “i” from the Core 3/5/7/9 differentiation scheme):
Chiplets are, as any of you who’ve been following tech news lately, one of the “hottest” things in semiconductors right now. And for good reason, as I wrote (for example) in my 2021 retrospective coverage on processor architectures, specifically about AMD in that case:
Some of AMD’s success is due to the company’s “chiplet” packaging innovations, which have enabled it to cost-effectively stitch together multiple die on a unified package substrate to achieve a given aggregate core count, cache amount and (in some cases) embedded graphics capability, versus squeezing everything onto one much larger, lower-yielding sliver of silicon.
The thing is, the chiplet concept isn’t particularly new. Multi-chip and multi-die modules under a single package lid, whether arranged side-by-side and/or vertically stacked, have been around for a long time. The chiplet implementation has only come to the fore now because:
- Leading-edge processes have become incredibly difficult and costly to develop and ramp into high-volume production,
- That struggle and expense, coupled with the exponentially growing transistor counts on modern ICs, have negatively (and significantly so) impacted large-die manufacturing yields not only during initial semiconductor process ramps but also long-term, and
- Desirable variability both in process technology (DRAM versus logic, for example), process optimization (low power consumption versus high performance) and IC sourcing (internal fab versus foundry), not to mention the attractiveness of being able to rapidly mix-and-match various feature set combinations to address different (and evolving) market needs, also enhance the appeal of a multi- vs monolithic-die IC implementation.
Chiplets are “old news” at this point for Intel’s competitors. As previously mentioned, AMD’s been doing them with its CPUs, GPUs and APUs (CPU-plus-GPU hybrids) since 2019’s Zen 2 microarchitecture-based Ryzen 3000 series. Similarly, Apple’s first homegrown silicon for computers, 2020’s M1 SoC, integrated DRAM alongside the processor die:
The belatedly-but-ultimately unveiled highest transistor count M1 Ultra variant further stretched the concept by stitching together two distinct M1 Max die via a silicon interposer:
And (cue irony) it’s not even a new concept to Intel itself. Way back in early 2005 (speaking of IDFs), Intel was playing catch-up with AMD, which was first to release a true single-die dual-core CPU, the Athlon 64 X2. Intel’s counterpunch, the Pentium D, stitched together two single-core CPU die, in this case interacting via a northbridge intermediary vs directly. Still, what’s old is new again, eh? Intel also leveraged multi-die, single package techniques in 2010’s “Arrandale” CPU architecture, for example, and more recently in the 47-“tile” Ponte Vecchio datacenter GPU.
Although at a high level the “song remains the same”, different chiplet implementations vary in key factors such as the inherent cost of the technology, the performance latency and power consumption of the interconnect, and the ability (or lack thereof) to pack together multiple die tightly both horizontally and vertically. Intel, for example, has branded its latest approaches as EMIB (the Embedded Multi-Die Interconnect Bridge, for 2D multi-die interconnect) and Foveros (for vertical multi-die stacking purposes). Here’s a brief video on the latter:
And all that commonality-or-not aside, Intel’s mixing-and-matching of different slivers of silicon from different fab sources using different process lithographies, not to mention the partitioning of functions among those various silicon slivers, is also intriguing. Meteor Lake comprises four main die, each with its own power management subsystem:
- The Compute tile, fabricated on the company’s own Intel 4 (7 nm EUV) process and integrating a varying mix of “P” (performance) and “E” (efficiency) processing cores. It’s reminiscent of the initial “hybrid” combinations in the company’s 12th generation “Alder Lake” CPUs, but these cores are generationally improved in metrics such as average and peak clock speed, power consumption in various modes, and IPC (the average number of instructions per clock cycle, for both single- and multi-threaded code).
- The SoC tile, fabricated on TSMC’s N6 (6 nm) process. It integrates a network-on-chip processor, thereby acting as the conductor for communication between the other tiles. It also integrates cores for silicon and system security, and for AI inference (I’m guessing the latter derives from Intel’s 2016 acquisition of Movidius, although that’s just an uninformed hunch). And interestingly, it also contains its own “E” processor cores, acting as a lowest-power-consumption compute tile alternative for relevant usage scenarios.
- The GPU tile, whose purpose is likely self-explanatory, is fabricated on TSMC’s N5 (5 nm) process and derived from the technology in the company’s latest Arc Xe discrete graphics processors. That said, the media codec and display controller functions normally found in a GPU aren’t included in this tile. Instead, they’re also in the aforementioned SoC tile.
- And, last but not least, the I/O tile, the smallest (area-wise) of the four, and the one most likely to be omitted from low-end Meteor Lake implementations. As its name implies, it implements “boutique” functions such as Thunderbolt 4. And at least initially, it’ll also be fabricated at TSMC, specifically (as with the SoC tile) on the N6 process.
Initial rumors suggested that initial Meteor Lake products, targeting mobile computing implementations, might show up in October. Whether that month was originally hoped-for or not inside Intel, the official “due date” for CPUs (and presumably also systems based on them) is now December 14, which pushes them out beyond both the holiday 2023 shopping cycle (for consumers) and 2024 budgetary cycle (for companies whose fiscal and calendar years coincide).
Why mobile first, versus desktop (or for that matter, server)? Mobile CPUs tend to prioritize low power consumption over peak performance and are also typically “kitted” with lower core counts than their desktop siblings, both attributes resonant with suppliers ramping up new die and packaged chip manufacturing processes. That said, Intel promises that desktop variants of Meteor Lake are also under development for production shipments beginning sometime next year. That said, and as presumed reassurance for skeptics, the company was already demoing its two-generations-subsequent desktop client CPU, 2025’s Lunar Lake, last week. And as for servers, Intel has a next-generation 144-core (“E”-only) monolithic Xeon CPU also coming out on December 14, with a dual-chiplet 288-core version to follow next year.
One final thing, returning once again to mobile. Not announced last week but sneak-peeked (then quickly yanked) a few weeks prior at a packaging event Intel put on was a Meteor Lake derivative with 16 GBytes of LPDDR5 SDRAM onboard for the ride, alongside the logic “tiles”.
If you’re thinking “Apple Silicon”, you’re conceptually spot-on, an association which Intel management is seemingly happy to encourage. 2024 and beyond should very interesting…
*I realize, by the way, that I may be dating myself with the title of this piece. How many of you are, like me, old enough to remember the Intel Inside branding program, now deprecated (as of, gulp, nearly 20 years ago) but apparently still with a pulse?
Thoughts as always are welcomed in the comments!
—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.