Image sensor embeds AI to explore image data

A new generation of CMOS image sensors can exploit all the image data to perceive a scene, understand the situation, and intervene by embedding artificial intelligence (AI) in the sensor. CEA-Leti researchers have reported this design breakthrough when demand for smart image sensors is growing rapidly due to their high-performance imaging capabilities in smartphones, automobiles, and medical devices.

The design breakthrough is built on a combination of hybrid bonding and high-density through silicon via (HD TSV) technologies, which facilitates the integration of various components like image sensor arrays, signal processing circuits and memory elements in image sensors with precision and compactness.

The design breakthrough is based on a three-layer test vehicle that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and with one wafer containing high-density TSVs. Source: CEA-Leti

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Communication between the different tiers in an image sensor design necessitates advanced interconnection technology. The new design presented by CEA-Leti employs hybrid bonding due to its very fine pitch in the micron and sub-micron range. It also uses HD TSV, which has a similar density that enables signal transmission through the middle tiers.

“The use of hybrid bonding and HD TSV technologies contribute to the reduction of wire length, a critical factor in enhancing the performance of 3D-stacked architectures,” said Renan Bouis, lead author of the paper titled “Backside Thinning Process Development for High-Density TSV in a 3-Layer Integration.” He added that stacking multiple dies to create 3D architectures, such as three-layer imagers, has led to a paradigm shift in sensor design.

The paper presents the key technological bricks that are mandatory for manufacturing 3D, multilayer smart imagers capable of addressing new applications that require embedded AI. “This sets the stage to work on demonstrating a fully functional three-layer, smart CMOS image sensor, with edge AI capable of addressing high-performance semantic segmentation and object-detection applications,” said Eric Ollier, project manager at CEA-Leti and director of IRT Nanoelec’s Smart Imager program.

The Grenoble, France-based research house CEA-Leti is a major partner of IRT Nanoelec, an R&D institute also based in Grenoble, France.

It’s worth mentioning that at ECTC 2023, CEA-Leti scientists reported a two-layer test vehicle combining a 10-μm high, 1-μm diameter HD TSV and highly controlled hybrid bonding technology, both assembled in F2B configuration. Now, they have shortened the HD TSV to 6-μm height, which led to the development of a two-layer test vehicle exhibiting low dispersion electrical performances and enabling simpler manufacturing.

It’s mainly due to an optimized thinning process that allowed the substrate thickness to be reduced with favorable uniformity. “This reduced height led to a 40% decrease in electrical resistance, in proportion with the length reduction,” said Stéphan Borel, lead author of the paper titled “Low Resistance and High Isolation HD TSV for 3-Layer CMOS Image Sensors”. “Simultaneous lowering of the aspect ratio increased the step coverage of the isolation liner, leading to a better voltage withstand.”

Scientists at CEA-Leti are confident that this smart image sensor technology will enable a variety of new applications.

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