Single supply 200kHz VFC with bipolar differential inputs



Few methods for analog to digital conversion are more “mature” than the classic combination of a voltage-to-frequency converter (VFC) with a counter. VFC digitization is naturally integrating, so good noise rejection is inherent, as is programmable resolution (if you want more bits, just count longer). Unfortunately, and for the same reason, high conversion speed is not. Accurate, high resolution, microsecond VFC conversion times are defiantly difficult, but at least millisecond rates are definitely doable as shown in this design idea. 

Nearly four decades ago (in his Designs for High Performance Voltage-to-Frequency Converters), famed analog guru Jim Williams cataloged five fundamental techniques for voltage to frequency conversion. First on his list, described as “most obvious”, was the “Ramp-Comparator” type. Since I’ve always been a big fan of the obvious, the simple VFC shown in Figure 1 is a variation on that basic theme. It’s adapted for operation from a single supply rail, with convenient and flexible differential bipolar inputs, and acceptable linearity while running at frequencies up to 200 kHz. Here’s how it works.

Figure 1 A Ramp-Comparator style 200 kHz VFC that operates from a single supply rail, with differential bipolar inputs, and an acceptable linearity.

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A2, R1, and Q2 combine to make a precision (Q2 α~0.998) current sink with Q2 collector current:

Ic2 = (V1 –V2)/R1 = 100µA(V1 –V2)

Non-inverting input V1 can range from 0 to (2 – V2), has a nicely high input impedance (>1 TΩ) and a low bias current (10 pA). Inverting input V2 has a lower impedance (10 kΩ) but will accept a voltage span from as positive as V1 to as negative as (V1 – 2). If only one input is used, the other should simply be grounded. Zero offset is about 200 µV (0.01%).

As shown in Figure 2 (yellow trace), Ic2 ramps 1-nF timing capacitor C1 from its reset voltage of 3.5 V down to the 2.5-V trigger level provided by voltage reference U1. The ramp time required to do this is given by:

T = C1(3.5 – 2.5)/Ic2 = C1R1/(V1 – V2)
= 1nF 10k/(V1 – V2) = 10µs/(V1 – V2)
Fout = 1/T = 100kHz (V1 – V2) < 200kHz

Figure 2 VFC oscillation waveshapes where: Vc1 is the VFC timing ramp, Fout is the output to counter, and A1p5 is the comparator’s non-inverting input.

Comparator A1’s inverting input is connected to C1, while its non-inverting input watches the 2.5-V reference. When the Vc1 ramp descends to 2.5 V, a sequence of (quite quick) events are set in motion.

First, A1’s output transitions toward 5 V, completing the move at 30 V/µsec in about 160 ns, the speed being enhanced by positive feedback via C4. This provides an output pulse (Figure 2 green trace) on Fout and turns on Q3 to begin the ramp-reset recharge of C1. Meanwhile C3 couples Q3’s output to D1, reverse biasing the diode and temporarily diverting Ic2 away from C1, which creates the funny little flat spots seen on Figure 2’s yellow and red traces. More on this later.

C1’s recharge current is routed via Q3’s emitter to Q1’s base, driving Q1 into saturation, accurately pulling R3’s top end to +5 V and thereby A1’s non-inverting input (pin 5) to 2.5(R5/(R3 + R5)) + 2.5 = 3.5 V (Figure 2 red trace). C1 recharge continues until A1 pin 5 reaches pin 6’s 3.5 V, whereupon A1 switches back to 0, turning off Q3 (fast because Q3 never saturates) and completing the Fout pulse.

Meanwhile, Q3’s turnoff has removed base drive from Q1, allowing it to recover from saturation (which takes about 500 ns consisting mostly of storage time), turn off, and release R3. This allows A1’s pin 5 to return to U1’s 2.5-V reference, where it waits for the end of the next timeout and VFC cycle.

It also dumps integrated Ic2 charge accumulated on C3 during ramp reset through D1 onto C1. The D1 C3 circuit feature thus cancels out an integral nonlinearity error that typically bedevils Ramp-Comparator VFCs due to charge lost during the ramp reset interval. Williams advises about this defect in his analysis of the Ramp-Comparator topology “A serious drawback to this approach is the capacitor’s discharge-reset time. This time, ‘lost’ in the integration, results in significant linearity error… The D1 C3 connection prevents this nonlinearity by allowing integration of Ic2 to continue uninterrupted during ramp reset, so no time is “lost”. Thanks for the warning, Jim!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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