Power Tips #133: Measuring the total leakage inductance in a TLVR to optimize performance

A trans-inductor voltage regulator (TLVR) modifies the conventional multiphase buck converter, accelerating the converter’s output current slew-rate speed capabilities to approach the fast load slew rate of the high-speed processor or application-specific integrated circuit’s core voltage rail. The output inductors each get a secondary winding, which are connected in series to create a secondary loop to accelerate the response to load changes. This improvement in load transient performance is at the cost of increased steady-state ripple and its resulting power loss, however. The problem is that it is very hard to estimate the actual overall inductance in the secondary loop, which is a primary driver of performance, as layout and printed circuit board (PCB) construction can significantly affect it. In this power tip, I will show a simple measurement that you can use to estimate actual leakage inductance in the TLVR secondary loop and optimize performance.

Figure 1 is a simplified schematic of the multiphase buck converter without and with the TLVR circuit.

Figure 1 Simplified multiphase buck converter and TLVR schematics. Source: Texas Instruments

Note the added secondary loop in the TLVR connecting all of the secondaries of the output inductors with the compensating inductor value, L_c, and parasitic elements shown. The sum of all of these inductances is the total secondary-loop inductance, or L_tsl. L_tsl determines TLVR performance, as both the added output current slew rate and high-frequency ripple current from the TLVR loop are inversely proportional to it. Because of the unpredictability of the parasitic inductances, when the TLVR was first introduced, it included a fixed L_c in the secondary loop.

The existing approach sets L_c to “swamp out” the parasitic inductances, assuming that they are much less than L_c. But there is a scope measurement across L_c that either will verify this assumption, or if not, provide the information you need to estimate the L_tsl. You can then adjust L_c to better match the target overall leakage for best slew-rate capability and ripple current performance, and in some cases omit it.

The TLVR performance equation is the output current slew-down capability ΔI/Δt in amperes per microseconds (A/µs), with some recent applications asking for as much as 5,000 A/µs. Slew-up capability is just as important, but with V_IN (12 V typically) generally much greater than V_OUT (0.7 V to 1.8 V typically), the slew-up rate capability will generally be much greater, and potentially excessive. Limiting how many phases you can turn on at the same time will usually reduce excessive slew-up capability.

The equations in Table 1 show that the load slew-rate acceleration is inversely proportional to L_tsl. Table 2 shows that the high-frequency TLVR currents are also inversely proportional to L_tsl.

Buck slew down ΔI/Δt		L is the value of the discrete output inductor at each stage
TLVR slew down ΔI/Δt		Lm is the value of the magnetizing inductance at each stage
Ltsl	(Assuming that Ltsl = Lc [1])	LLeakage is defined as the leakage inductance of each output inductor

Table 1 Buck and TLVR slew-down ΔI/Δt equations. Source: Texas Instruments

Time period where all phases are off (TOFF)		Fsw is the switching frequency of each phase
High frequency p-p current ripple (ΔILtsl)		In the secondary loop and in each power stage
Root-mean-square (RMS) value of this current

Table 2 TLVR high-frequency currents in the secondary winding and all phases when V_OUT ´ N_phases < V_IN. Source: Texas Instruments

Below in Table 3 are the expected voltages across L_c when V_OUT x N_phases < V_IN assuming L_tsl ≈ L_c, and recalculation of L_tsl when smaller voltages are seen.

Voltage across Ltsl (and Lc if Ltsl ≈ Lc) when one phase is on		Assuming the polarity of Lc as shown in Figure 1
Voltage across Ltsl (and Lc if Ltsl ≈ Lc) when all phases are off		Assuming polarity of Lc as shown in Figure 1
RMS of the waveform
Estimating Ltsl when the actual waveform is smaller than the expected waveform		Use calculated VLtslrms and measured VLcrms

Table 3 Expected voltage waveform across L_c when V_OUT x N_phases < V_IN assuming L_tsl ≈ L_c, and recalculation of L_tsl when smaller voltages are seen. Source: Texas Instruments  

Now it’s time to introduce a design example, starting with the requirements and overall approach, as shown in Table 4. 

Table 4 Design requirements and overall approach. Source: Texas Instruments

 This 32-stage design uses two TLVR loops each at the near-5-MHz sawtooth frequency, but 180 degrees out of phase in order to achieve good but imperfect cancellation of the sawtooth waveforms in the output capacitors. Without TLVR, even with 32 phases and inductors at only 70 nH, the fastest slew-down rate would be 460 A/µs. Based on the equations in Table 2, the slew-down capability would be -5,387 A/µs. Getting this >5,000 A/µs slew-rate capability requires accepting a high-frequency ripple current in each phase of 3.4 A_RMS.

I tested a board built up with the assumption that L_tsl ≈ L_c and used 100 nH the target L_tsl for L_c. Figure 2 shows the layout of one of the two TLVR loops.

Figure 2 The layout of a 16-power-stage TLVR loop. Source: Texas Instruments

But is the 100-nH L_c really the true L_tsl of this 16-stage loop? See the large secondary loop between “start” and “end” in Figure 2. Measuring the actual voltage waveform across L_c (L36 here) when all 16 stages and eight phases are active sheds light on this assumption. If L_tsl ≈ L_c and using the formulas from Table 3, you should expect a square wave going between +8 V and -16 V at eight times the per-phase switching frequency. The RMS value of this waveform should be 11.3 V.

Figure 3 shows what I actually measured.

Figure 3 Measured voltage waveform across an eight-phase/16-stage compensating inductor with expected TLVR waveform if L_tsl ≈ L_c, shown in black. Source: Texas Instruments

Both the actual L36 waveform (pink) versus the expected total leakage waveform (black) and the RMS value (5.02 V versus 11.3 V) point to L_c being one-half the L_tsl and point to that fact that there is another 100 nanohenries from inductor leakages and PCB traces in the secondary loop. Comparing the actual versus expected RMS values instead of peak values will reduce the confusion introduced by the parasitic ringing evident on the measured waveform.

With the total inductance in the secondary loop at 200 nH, the output current slew-down capability is reduced to -2,827 A/µs for the 32-stage design. For the 5,000 A/µs load slew-rate application, shorting out the actual L_c reduced the total secondary inductance back to 100 nH. For applications with a maximum load slew rate less than 3,000 A/µs, leaving the compensating inductors in place will reduce circulating high-frequency currents by half and reduce losses from these currents by 75%.

Obtaining leakage inductance

Knowing the actual leakage inductance in your TLVR loop will put you in the best position to get your output current slew rate while minimizing added losses caused by the TLVR loop. Discovering that one simple measurement will give you the necessary information is one example of what my colleagues and I pursue at Texas Instruments in the interests of power-management optimization.

Josh Mandelcorn has been at Texas Instrument’s Power Design Services team for almost two decades focused on designing power solutions for automotive and communications / enterprise applications. He has designed high-current multiphase converters to power core and memory rails of processors handling large rapid load changes with stringent voltage under / overshoot requirements. He previously designed off-line AC to DC converters in the 250 W to 2 kW range with a focus on emissions compliance. He is listed as either an author or co-author on 17 US patents related to power conversion. He received a BSEE degree from the Carnegie-Mellon University, Pittsburgh, Pennsylvania.

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References

1. Schurmann, Matthew, and Mohamed Ahmed. “Introduction to the Trans-inductor Voltage Regulator (TLVR).” Texas Instruments Power Supply Design Seminar SEM2600, literature No. SLUP413. 2024-2025.

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