A recent design idea, “Negative time-constant and PWM program a versatile ADC front end,” offered a pretty peculiar ADC front end (see Figure 1). It comprises a programmable gain (PG) instrumentation amplifier (INA). It uses PWM control of a flying capacitor to implement a 110-dB CMRR, high impedance differential input and negative time-constant exponential amplification with more than 100 discrete programmable gain steps. It’s then topped off with a built-in sample and hold (S&H). Hence PGINASH. Catchy. Ahem.

Figure 1 PGINASH: An unconventional ADC front end with INA inputs, programmable gain, and sample and hold.

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Due to A1c’s gain of (R3 / R2 + 1) = 2, during the PWM = 1 gain accumulation phase the connection established from U1c’s output through U2a and R1 to C creates positive feedback that makes the voltage captured on C multiply exponentially with a (negative) time-constant Tc of (nominally):

Tc = R1*(C + Cstray) =
= 14.3k*(0.001µF + (8pF (from U2a) + 1pF (from U1c)))
= 14.3k*1009pF = 14.43µs
= 10µs / ln(2)
G = gain increment of 2^0.1= 1.0718 = 0.6021dB per us of accumulation time T
G¹⁰= 2.0 = 6.021dB per 10µs of T
This combines with A1c’s fixed gain of two to total
Nominal net Gain = 2G^T/10µs

Of course, the keyword here is “nominally.” Both R1 and C will have nonzero tolerances, perhaps as poor as ±1%, and ditto for R2 and R3. Moreover, further time-constant, and therefore gain, error can arise from U2 switch to switch ON resistance mismatches. The net bad news, pessimistically assuming worst case mutual error reinforcement of all the time-constant component tolerances, is A1c’s gain may vary by ±2% and G by as much as ±3%. This is far from adequate for precision data acquisition! What to do?

The following sequence is suggested as a simple software-based in-circuit calibration method using a connected ADC and requiring just two calibration voltages to be manually connected to the IA inputs as calibration progresses, to combat the various causes of front-end error.

GAIN ERROR

The first calibration voltage (Vcal) is used to explicitly measure the as-built gain factors. Here’s how it works:

Vcal = Vfs/Vheadroom
where
Vfs = ADC full-scale Vin
Vheadroom = (2*1.02)*(2*1.04)² = 8.8
e.g., if Vfs = 5v, Vcal = 0.57v

Vcal’s absolute accuracy isn’t particularly important, +/-1% is plenty adequate. But it should be stable to better than 1 lsb during the calibration process. Connect Vcal to the INA inputs, then take two ADC conversions: D1 with gain accumulation time T =10 µs and D2 with T = 20 µs. Thus, if 2^x= the as-built A1c gain and G = the as-built exponential gain, the ADC will read:

D1 = ADC(2^x*G¹⁰*Vcal)
D2 = ADC(2^x*G¹⁰*G¹⁰*Vcal)

Averaging a number (perhaps 16) acquisitions of each value is probably a good idea for best accuracy. The next step is some arithmetic:

D2/D1 = (2^x*G¹⁰*G¹⁰*Vcal)/(2^x*G¹⁰*Vcal) = G¹⁰
D1/ (G¹⁰*Vcal) = (2^x*G¹⁰*Vcal)/(G¹⁰*Vcal) = 2^x
G = (G¹⁰)^0.1

That wasn’t so bad, was it? Now we if we want to set (most) any desired conversion gain of Y, we just need to compute a gain accumulation interval of:

T(µs) = log(Y/2^x)/log(G)

Note if that this math yields T < 1 µs, we’ll need to bump Y for some extra time (and gain) to allow for capacitor “flight” and signal acquisition.

INPUT OFFSET ERROR

There is, however, another error source we haven’t covered: U1 input offsets. Although the TLV9164 typical offset is only 200 µV, max can range as high as 1.2 mV. If uncorrected, the three input amplifiers’ offsets could sum to 3.6 mV. This would render the upper gain range of our amplifier of little value. To fix it, we need another input voltage reference (Vzero), some more arithmetic, and another ADC conversion to measure the Voff offset and allow software subtraction. We’ll use lots of gain to get plenty of resolution. Vzero should ideally be accurate and stable to <10 µV to take full advantage of the 9164’s excellent 0.25 µV/^oC drift spec’.

Let Vzero = 4.00mV
N = log(Vfs/(.008v * 2^x))/log(G)
D3 = ADC(2^x*G^N*(Vzero + Voff))
Voff = D3/(2^x*G^N) – Vzero

And there you have it. To accurately massage any raw ADC result into the actual Vin input that produced it, write:

Vin = (ADC(Vin)/(2^x G^N)) – Voff

But avoid G^N> Vfs /(2^x*Voff). Otherwise A1c and the ADC may be driven into saturation by amplified offset. Also, things may (okay, will) get noisy.

Okay. But what about…

LEAKAGE CURRENT ERROR

The leakage current conundrum comes from the fact that negative time-constant current from U1c through R1 isn’t the only source of gain-phase charge for C. Unfortunately, leakage currents from U2’s X pin and U1’s noninverting input also contribute a mischievous share. U1’s contribution is a negligible 10 pA or so, but U2’s can be large enough to become problematic.

The burning question is: How much do HC4053 switches really leak? Reeeeeally? Datasheets are of surprisingly little help, with the answer seeming to range over literally a million-to-one, pA to µA, range.

Figure 2 quantifies the result for some plausible 100 pA to 1 µA numbers.

Figure 2 The input referred current – equivalent voltage offsets.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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