Visual security systems have evolved enormously since the days of infrared motion detectors and laser tripwires. Today, high-definition cameras stream video into local vision-processing systems. These AI-enabled surveillance cameras detect motion, isolate and identify objects, capture faces, expressions, and gestures, and may even infer the intent of people in their field of view. They record interesting videos and forward any significant events to a central security console.
Integrating AI capabilities transforms security cameras into intelligent tools to detect threats and enhance surveillance proactively. Intent inference, for example, allows security cameras to quickly predict suspicious behavior patterns in crowds, retail stores, and industrial facilities. Case in point: AI-enabled cameras can detect unattended packages, license plates, and people in real time and report them to security personnel.
According to a report from Grandview Research, due to the evolving use of AI technology and growing security concerns, the market for AI-enabled security cameras is projected to grow at a CAGR of over 18% between 2024 and 2032. This CAGR would propel the market from $7.55 billion in 2023 to $34.2 billion in 2032.
The need for compute power
Increasing sophistication demands growing computing power. While that antique motion sensor needed little more than a capacitor and a diode, real-time object and facial detection require a digital signal processor (DSP). Advanced inferences such as expression or gesture recognition need edge AI: compact, low-power neural-network accelerators.
Inferring intent may be a job for a small-language model with tens or hundreds of millions of parameters, demanding a significantly more powerful inference engine. Less obviously, this growth in functionality has profound implications for the security camera’s local non-volatile storage subsystem. Storage, capacity, performance, reliability, and security have all become essential issues.
Storage’s new role
In most embedded systems, the storage subsystem’s role is simple. It provides a non-volatile place to keep code and parameters. When the embedded system is initialized, the information is transferred to DRAM. In this use model, reading happens only on initialization and is not particularly speed sensitive. Writing occurs only when parameters are changed or code is updated and is, again, not performance sensitive.
The use case for advanced security cameras is entirely different. The storage subsystem will hold voluminous code for various tasks, the massive parameter files for neural network models, and the continuously streaming compressed video from the camera.
To manage energy consumption, designers may shut down some processors and much of the DRAM until the camera detects motion. This means the system will load code and parameter files on demand—in a hurry—just as it begins to stream video into storage. So, both latency and transfer rate are essential.
In some vast neural network models, the storage subsystem may also have to hold working data, such as the intermediate values stored in the network’s layers or parameters for layers not currently being processed. This will result in data being paged in and out of storage and parameters being loaded during execution—a very different use model from static code storage.
Storage meeting new needs
Except in scale, the storage use model in these advanced security cameras resembles less a typical embedded-system model than what goes on in an AI-tuned data center. This difference will impose new demands on the camera’s storage subsystem hardware and firmware.
The primary needs are increased capacity and speed. This responsibility falls first upon the NAND flash chips themselves. Storage designers use the latest multi-level and quad-level, stacked-cell NAND technology to get the capacity for these applications. And, of course, they choose chips with the highest speeds and lowest latencies.
However, fast NAND flash chips with terabit capacity can only meet the needs of security-camera applications if the storage controller can exploit their speed and capacity and provide the complex management and error correction these advanced chips require.
Let’s look at the storage controller, then. The controller must support the read-and-write data rates the NAND chips can sustain. And it must handle the vast address spaces of these chips. But that is just the beginning.
Storage controller’s tasks
Error correction in NAND flash technology is vital. Soft error rates and the deterioration of the chips over time make it necessary to have powerful error correction code (ECC) algorithms to recover data reliably. Just how important, however, is application dependency? A wrong pixel or two in a recorded video may be inconsequential. Neural network models can be remarkably tolerant of minor errors.
But a bad bit in executable code can turn off a camera and force a reboot. A wrong most significant bit (MSB) in a parameter at a critical point in a neural network model, especially for small-language models, can result in an incorrect inference. So, a mission-critical security camera needs powerful, end-to-end error correction. The data arriving at the system DRAM must be precisely what was initially sent to the storage subsystem.
This requirement becomes particularly interesting for advanced NAND flash chips. Each type of chip—each vendor’s process, number of logic levels per cell, and number of cells in a stack—will have its error syndromes. Ideally, the controller’s ECC algorithms will be designed for the specific NAND chips.
Aging is another issue—flash cells wear out with continued reading and writing. However, as we have seen, security cameras may almost continuously read and write storage during the camera’s lifetime. That is the worst use case for ultra-dense flash chips.
To make matters more complex, cameras are often mounted in inaccessible locations and frequently concealed, so frequent service is expensive and sometimes counterproductive (Figure 1). The video they record may be vital for safety or law-enforcement authorities long after it is recorded, so degradation over time would be a problem.
Figure 1 Managing flash cell endurance is an essential issue since cameras are often mounted in inaccessible locations. Source: Silicon Motion
The controller’s ability to distribute wear evenly across the chips, scrub the memory for errors, and apply redundant array of independent disks (RAID)-like techniques to correct the mistakes translates into system reliability and lower total cost of ownership.
To counter these threats, the storage controller must be forearmed. Provisions should be made for fast checkpoint capture, read/write locking of the flash array, and a quick, secure erase facility in case of power loss or physical damage. To blunt cyberattacks, the storage subsystem must have a secure boot process, access control, and encryption.
A design example
To appreciate the level of detail involved in this storage application, we can focus on just one feature: the hybrid zone. Some cells in a multi-level or quad-level NAND storage can store only a single bit of data instead of two or four bits. The cells used as single level are called hybrid zones. They will have significantly shorter read and write latencies than if they were being used to store multiple bits per cell.
The storage controller can use this feature in many ways. It can store code here for fast loading, such as boot code. It can store parameters for a neural network model that must be paged into DRAM on demand. For security, the controller can use a hybrid zone to isolate sensitive data from the access method used in the rest of the storage array. Or the controller can reserve a hybrid zone for a fast dump of DRAM contents in case of system failure.
Figure 2 Here is how the FerriSSD controller offers a hybrid zone, the unique capability of partitioning a single NAND die into separate single-level cells (SLC) and multi-level cells/3D triple-level cells (MLC/TLC zones). Source: Silicon Motion
The hybrid zone’s flexibility ultimately supports diverse storage needs in multi-functional security systems, from high-speed data access for real-time applications such as authentic access to secure storage for critical archived footage.
Selecting storage for security cameras
Advanced AI security cameras require a robust storage solution for mission-critical AI video surveillance applications. Below is an example of how a storage controller delivers enterprise-grade data integrity and reliability using ECC technology.
Figure 3 This is how a storage controller optimizes the choice of ECC algorithms. Source: Silicon Motion
The storage needs of advanced security cameras go far beyond the simple code and parameter storage of simple embedded systems. They increasingly resemble the requirements in cloud storage systems and require SSD controllers with error correction, reliability, and security features.
This similarity also places great importance on the controller vendor’s experience—in power-conscious edge environments, high-end AI cloud environments, and intimate relationships with NAND flash vendors.
Lancelot Hu is director of product marketing for embedded and automotive storage at Silicon Motion.
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