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The advanced-packaging needs of AI chips are driving a move by the semiconductor tool and material industry to supply rectangular panels aimed at taking market share from the round silicon wafers we are all so familiar with.
Toolmakers Lam Research and Nikon are among companies selling components for panel production, with an expected business takeoff starting as early as 2027, according to Lam.
Top foundry TSMC, which has dominated advanced packaging of AI chips for customers like Nvidia and AMD, is likely to yield its hegemony of heterogeneous integration to OSATs (outsourced semiconductor assembly and test companies) that are preparing to grab more of the business, according to Lam.
The total panel-level packaging (PLP) business, which today supports PCB and flat-panel display production, is set to soar from $160 million in 2024 to $650 million by 2030, driven by high-performance computing (HPC) and AI demand, according to a March report from Yole Group. Established PLP players like Samsung and top chip packager ASE are joined by newcomers Amkor, Japanese startup foundry Rapidus and even TSMC, which may roll out its tech within three years for high-end fan-out packaging, the report said.
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Lam has been developing interconnect for panels ranging from 300 mm to 600 mm, Lam Managing Director Chee Ping Lee told EE Times in an interview.
“The talk in the industry now is: if I were to do the fabrication of the packaging structure on a panel, you don’t have to stop at 300, you can go to as large as 600,” Lee said. “Then you put more die on one package and process it on one single system.”
Advanced packaging at the 2.5D and 3D level, where chips are stacked like flats in a residential building block, has been the exclusive domain of foundry TSMC, which has the costly cleanroom space that low capital-intensity chip packagers lack. That’s about to change, now that chip packagers like ASE and Amkor are boosting investment in high-end facilities.
“We announced our plans in 2023 and are working closely with federal and state government agencies, supply chain partners and customers,” Amkor told EE Times in an emailed statement. “We remain on track for full operations in early 2028, which reflects the complex nature of establishing advanced manufacturing capabilities at this scale.”
On Oct. 7, second-ranked chip packager Amkor more than tripled its investment in the U.S. state of Arizona to $7 billion, close to new megafab projects run by TSMC and Intel. The expanded investment will result in over 750,000 square feet of cleanroom space at the new Amkor facility in early 2028.
“We do see advanced packaging becoming more broadly adopted, gaining more industry players, including OSATs, large and mid-sized,” Lam’s Lee said. “Some OSATs see it as a way to climb up the value chain. The larger ones will be able to climb it.”
In September, Lam introduced its Teos 3D tool for 3D stacking and high-density heterogeneous integration. The company said the tool provides ultra-thick, uniform, inter-die gapfill, innovations in dielectric deposition and enhanced monitoring tech. Lam said its systems have been installed at leading logic and memory fabs around the world.
Shift to panels
AI chips are growing so large that they exceed the maximum reticle size of chipmaking tools, limiting transistor density and I/O connections, increasing costs and reducing yield on silicon wafers.
The architecture for Nvidia’s AI Blackwell is a two-reticle package, meaning that the chips each have an area of approximately 800 mm2, raising the issue of how to fit the rectangular chips on a round 300 mm wafer, according to a report by ACM Research.
With a chip size of ~800 mm2, you can fit approximately 64 chips on a round 300 mm wafer, the report said. “However, as the chip is square and the wafer is round, a significant amount of silicon goes to waste in processing the chip,” the report noted.
Silicon wafers are round because they are cut from cylindrical silicon ingots, made in a process as old as the dipping of a wax candle.
The inflection point for panels will come in a few years when reticle sizes reach 4,500 mm2, according to Lam. When reticle sizes exceed 7,700 mm2, around 2030, panels will become a more attractive option as AI chip interposers, Lee said.
Lam is working with the industry ecosystem, including chip designers and research institutions to co-optimize processes. The disruption may create a new ecosystem.
“The suppliers will change from the typical silicon carriers to glass carriers, new players you might not have heard of three to four years ago,” Lee said, declining to name companies. “Panels are in production today. For example, the 600 mm size is in low-volume production for low-end chips, RF chips. For AI chips, that’s still in development, and it will take some time.”
Lam sees competition from foundries to substrate makers.
“The final ecosystem, what it will look like, is uncertain,” Lee said. “Multiple sizes are coming from different players. There is a lack of standardization. We do expect in the long run, standardization will happen.”
New suppliers
One potential new panel supplier is glass substrate maker Absolics, an affiliate of South Korea-based SKC. The company made headlines in May 2024 when it won a $75 million CHIPS Act grant from the U.S. government to invest in a substrate facility in the U.S. state of Georgia.
At the time, Absolics said its glass substrates will boost performance of chips for AI, HPC and data centers.
The company didn’t respond to EE Times’ request for comment.
Major companies in the supply chain have announced their entry to the panel business.
Nikon in July started taking orders for its Digital Lithography System DSP-100. The system is specifically developed for advanced packaging applications, supporting large substrates up to 600 mm2.
For 100 mm2 large packages, productivity per substrate is nine times higher than when utilizing 300 mm wafers, Nikon said on its website.
“Additionally, the system offers high-precision correction for substrate warpage and deformation, reducing production costs with maskless technology and minimizing maintenance costs with solid-state light sources, supporting greener manufacturing,” Nikon said.
Applied Materials is also making tools for panel processing.
“Silicon is a great substrate material, but wafers are round, so you can only make a small number of rectangular AI accelerators per substrate,” Amulya Athayde, senior director of strategic marketing at Applied’s Heterogeneous Integration Business Unit, told EE Times.
The company provides a suite of panel-processing tools with front-end patterning for packaging applications – including lithography, PVD, CVD, metrology, pattern review and testing.
“Based on our experience with handling large form-factor substrates for the display tool market, Applied is in a unique position to scale wafer processing technology to the panel scale,” Athayde said.
