The relentless pursuit of higher performance and greater functionality has propelled the semiconductor industry through several transformative eras. The most recent shift is from traditional monolithic SoCs to heterogeneous integrated advanced package ICs, including 3D integrated circuits (3D ICs). This emerging technology promises to help semiconductor companies sustain Moore’s Law.
However, these advancements bring increasingly complex challenges, particularly in power integrity (PI) and signal integrity (SI). Once secondary, SI/PI have become critical disciplines in modern semiconductor development. As data rates ascend into multiple gigabits per second and power requirements become more stringent, error margins shrink dramatically, making SI/PI expertise indispensable. The fundamental challenge lies in ensuring clean and reliable signal transmissions and stable power delivery across intricate systems.
Figure 1 The above diagram highlights the basic signal integrity (SI) issues. Source: Siemens EDA
This article explains the unique SI/PI challenges in 3D IC designs by contrasting them with traditional SoCs. We will then explore a progressive verification strategy to address these complexities, examine the roles and interdependencies of stakeholders in the 3D IC ecosystem, and illustrate these concepts through a real-world success story. Finally, we will discuss how these innovations drive the future of semiconductor design.
Traditional SI/PI versus 3D IC approaches
In traditional SoC components destined for a PCB system, SI and PI analysis typically validates individual components before system integration. This often treats SoCs, packages, and PCBs as distinct entities, allowing sequential analysis and optimization. For instance, component-level power demand analysis can be performed on the monolithic SoC and its package, while signal integrity analysis validates individual channels.
The design process is often split between separate packaging and PCB teams working in parallel. These teams eventually collaborate to manage design trade-offs such as allocating timing or voltage margins between the package and PCB to accommodate routing constraints. While effective for traditional designs, this compartmentalized approach is inadequate for the inherent complexities of 3D ICs.
A 3D IC’s architecture is not merely a collection of components but a highly condensed system of mini subsystems, characterized by the vertical stacking of multiple dies. Inter-die interfaces, through-silicon vias (TSVs), and microbumps create a dense, highly interactive electrical environment where power and signal integrity issues are deeply intertwined and can propagate across multiple layers.
The tight integration and proximity of the dies introduce novel coupling mechanisms and power delivery challenges that cannot be effectively addressed by sequential, isolated analyses. Therefore, unlike a traditional flow, 3D ICs demand holistic, parallel validation from the outset, with SI and PI analyses commencing early and encompassing all constituent parts concurrently.
Progressive verification
To navigate the intricate landscape of 3D IC design, a progressive verification strategy is paramount. This principle acknowledges that design information is sparse in early stages and becomes progressively detailed.
The core idea behind progressive verification is to initiate analysis as early as possible with available inputs, guiding the design onto the correct path and transforming the final verification step into confirmation rather than a discovery of fundamental issues. Different analysis requirements are addressed as details become available, starting with minimal inputs and gradually incorporating more specific data.
Figure 2 Here is a view of a progressive verification flow. Source: Siemens EDA
Let’s summarize the various analyses involved and their timing in the design flow.
Early architectural feasibility and pre-layout analysis
At the initial design phase, before detailed layout information is available, the focus is on architectural feasibility studies. This involves estimating power budgets and defining high-level interfaces. Even with rough inputs, early analysis can commence. For instance, pre-layout signal integrity analysis can model representative interconnect structures, such as an interposer bridge.
By defining an “envelope” of achievable performance based on preliminary dimensions, designers can establish realistic expectations and guidelines for subsequent layout stages. This proactive approach helps identify potential bottlenecks and ensures a robust electrical foundation.
Floorplanning and implementation-driven analysis
As the design progresses to floorplanning and initial implementation, guidelines from early analysis are translated into a physical layout. At this stage, more in-depth analyses become possible. This includes detailed power delivery network (PDN) analysis to verify power distribution across stacked dies and the substrate.
Signal path verification with actual component interconnections can also begin, enabling early identification and optimization of critical signal routes. This iterative process of layout and analysis enables continuous refinement, ensuring physical implementation aligns with electrical performance targets.
Detailed electrical analysis with vendor-specific IP
The final stage of progressive verification involves comprehensive electrical analysis utilizing actual vendor-specific intellectual property (IP) models. Given the nascent state of 3D IC die-to-die standards—for instance UCIe, BoW, and AIB, which are less mature than established protocols like DDR or PCIe—this detailed analysis is even more critical.
Designers perform in-depth S-parameter modeling of impedance networks, feeding these models with precise current values obtained from die designers and other stakeholders. This granular analysis provides full closure on the design’s electrical performance, ensuring all critical signal paths and power delivery mechanisms meet specifications under real-world operating conditions.
The 3D IC ecosystem
The complexity of 3D IC designs necessitates a highly collaborative environment involving diverse stakeholders, each with unique perspectives and challenges. Effective communication and early engagement among these teams are crucial for successful integration.
- System architects are responsible for the high-level floorplanning, determining the number of chiplets, baseband dies, and the communication channels required between them. Their challenge lies in optimizing the overall system architecture for performance, power, and area, while considering the physical constraints imposed by 3D integration.
- Die designers focus on individual die architectures and oversee I/O planning and internal power distribution. They must communicate their power requirements and I/O characteristics accurately to ensure compatibility within the stacked system. Their primary challenge is to optimize the die-level performance while adhering to system-level constraints and ensuring robust power and signal delivery across the interfaces.
- Layout teams are responsible for the physical implementation, encompassing die-level layout, substrate layout, and silicon interconnects like interposers and bridges. Often different layout teams may handle different aspects of the implementation, requiring meticulous coordination. Their challenges include managing extreme density, minimizing parasitic effects, and ensuring manufacturability across multiple layers.
- SI/PI and verification teams act as technical consultants, providing guidelines and feedback at every level. They advise system architects on bump-out strategies for die floorplans and work with die designers to optimize power and ground bump counts. Their role is to proactively identify and mitigate potential SI/PI issues throughout the design cycle, ensuring that the electrical performance targets are met.
- Mechanical and thermal teams ensure structural integrity and manage heat dissipation, respectively. Both are critical for the long-term reliability and performance of designs, as beyond electrical considerations, 3D ICs introduce significant mechanical and thermal challenges. For example, the close proximity of die can lead to localized hotspots and mechanical stresses due to differing coefficients of thermal expansion.
By employing a progressive verification methodology, these diverse stakeholders can engage in early and continuous communication, fostering a collaborative environment that makes it significantly easier to build a functional and reliable 3D IC design.
Chipletz’s proof of concept
The efficacy of a progressive verification strategy and collaborative ecosystem is best illustrated through real-world applications. Chipletz, a fabless substrate startup, exemplifies successful navigation of 3D IC design complexities in collaboration with an EDA partner. Chipletz is working closely with Siemens EDA for its Smart Substrate products, utilizing tools capable of supporting advanced 3D IC design requirements.
Figure 3 Smart Substrate uses cutting-edge chiplet integration technology that eliminates an interposer. Source: Siemens EDA
At the time, many industry-standard EDA tools were primarily tailored for traditional package and PCB architectures. Chipletz presented a formidable challenge: its designs featured massive floorplans with up to 50 million pin counts, demanding analysis tools with unprecedented capacity and layout tools capable of handling such intricate structures.
Siemens responded by engaging its R&D teams to enhance tool capacities and capabilities. This collaboration demonstrated not only the ability to handle these complex architectures but also to perform meaningful electrical analyses on such large designs. Initial efforts focused on fundamental aspects such as direct current (DC) IR drop analysis across the substrate and early PDN analysis.
Through these foundational steps, Siemens demonstrated its tools’ capabilities and, crucially, its commitment to working alongside Chipletz to overcome challenging roadblocks. This partnership enabled Chipletz to successfully tape out its initial demonstration vehicle, and it’s now progressing to the second revision of its design. This underscores the importance of adaptable EDA tools and strong collaboration in pushing the boundaries of 3D IC innovation.
Driving 3D IC innovation
3D ICs are unequivocally here to stay, with major semiconductor companies increasingly incorporating various forms of 3D packaging into their product roadmaps. This transition signifies a fundamental shift in how the industry approaches system design and integration. As the industry continues to embrace 3D IC integration as a key enabler for next-generation systems, the methodologies and collaborative approaches outlined in this article for SI and PI will only grow in importance.
The progressive verification strategy, coupled with close collaboration among diverse stakeholders, offers a robust framework for navigating the complex challenges inherent in 3D IC design. Companies and individuals who master these techniques will be exceptionally well-positioned to lead the next wave of semiconductor innovation, creating the high-performance, energy-efficient systems that will power our increasingly digital world.
Todd Burkholder is a senior editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.
John Caka is a signal and power integrity applications engineer with over a decade of experience in high-speed digital design, modeling, and simulation. He earned his B.S. in electrical engineering from the University of Utah in 2013 and an MBA from the Quantic School of Business and Technology in 2024.
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