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A London, U.K.-based startup has emerged from stealth with a mission to reduce the time it takes to design next-generation chips from years to weeks by using AI in the process of converting system RTL to GDSII. Tattvam AI, which has received $1.7 million from early investors, including veteran entrepreneur Stan Boland, has begun initial discussions with customers and plans to raise a larger round later this year.
In a briefing with EE Times, co-founder Bragadeesh S. emphasized that the chip design process is slow despite the billions of dollars spent on global R&D. He said that parts of the physical design process (in which you convert the RTL code created by design tools into the final GDSII file for tape-out) can take months at a time, each with several iterations, resulting in two-to-three-year design cycles for complex chips.
Physical design involves everything from floor planning, placement, and routing to clock tree synthesis (CTS), power planning, and design rule checking. According to Bragadeesh, even seemingly simple tasks like timing closure and CTS in physical design can take months due to iterative loops. Aligning communications between different teams working on different parts of the physical design slows down the entire process even more.
Bragadeesh said that Tattvam AI is addressing this by building a local AI system that can understand the circuit and suggest actions and insights in just a few hours based on design goals. He calls it the intelligence layer for chip design, where Tattvam AI is training an AI tool to understand circuits from first principles and autonomously solve the design problems that today consume years of expert engineering time.
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He said that physical design is one of the most labor-intensive stages of the chip development process, in which engineers manually navigate thousands of interdependent decisions around placement, routing, and timing, with each iteration taking weeks. Tattvam AI aims to build a reasoning engine to eliminate this bottleneck, with the ambition of compressing processes that currently take years into a matter of weeks.
“Chip design is fundamentally a reasoning problem over an enormous search space, not unlike the kind of reasoning that’s needed to solve hard problems in mathematics. Current AI tools, even the most advanced LLMs, struggle with the deep structural understanding that chip design demands,” Bragadeesh said in prepared remarks. “We’re building a reasoning model that actually understands circuits from first principles—the constraints, the tradeoffs, the interdependencies—the same way a world-class engineer would, and doing it in a fraction of the time.”
He told EE Times that the tool is expected to launch in a few months, but wasn’t specific as to what will be included at launch. “We have identified a specific wedge in physical design, where the problem structure is relatively well defined, and engineers currently spend a lot of time,” he said. “I can hint that the initial area will focus on timing closure-type challenges. I also think many techniques translate, that’s why we’ll look to scale from our wedge to multiple aspects of physical design after that. Our focus is to ensure the product integrates well within a customer environment, optimizing for AI thinking time and the customer’s data confidentiality requirements.”
When we met him in London a few weeks ago, you could see that Bragadeesh had real depth of knowledge and understanding of the challenge here, especially with several of the hyperscalers trying to do their own custom chips, and the bottlenecks they face in chip design. As is widely recognized in industry, designing a chip from scratch takes two to three years and costs tens of millions of dollars before a single one rolls off a fab.
Catching even a single design error in the later stages can mean months of delays and a $50 million respin. “The tools chip engineers use, called EDA software, handle the mechanics of design, but the hardest decisions still require expert engineers manually iterating through thousands of possibilities,” the company said in its press release.
There was emphasis in our discussion that Tattvam AI’s local AI system isn’t intended to compete with existing EDA tools from the major vendors, such as Synopsys or Cadence, but to dovetail into existing workflows. Where it will impact is the design services companies that employ hundreds of engineers to build the chips as a turnkey offering for ASIC design services, such as Alchip Technologies, Aion Technology (formerly Sondrel), and Ensilica.
On the technology itself, Bragadeesh said they use learnings from open-source AI to solve abstract reasoning tasks, such as ARC-AGI, to build an AI tool that deeply understands a given circuit and performs tasks like a human engineer. The company uses synthetic datasets inspired by ARC-AGI benchmarks and mathematical theorems to train domain-specific models at low cost. This enables the replication of real chip tape-out processes and the generation of high-quality training data.
Still early on its journey, but strong conviction and backing
The company just came out of stealth this week and announced a $1.7 million investment, but has yet to launch its product. So why should we take note of a two-person startup so early on?
Well, as most investors say, one key characteristic is the founders’ passion. Co-founder Bragadeesh certainly oozes passion and energy. He may be young, but after graduating from IIT Madras in India and stints at Texas Instruments and Imagination Technologies, he then built a compute device to process brain signals in real time at CoMind, went on to be a member of the technical staff at Fractile, and then turned down a role at Google’s TPU team to start Tattvam AI.
Second is the backing, with pre-seed funding of $1.7 million from Seedcamp, EWOR, Entropy Industrial Capital, Concept Ventures, and semiconductor angel investor and entrepreneur Stan Boland.
“Bragadeesh is one of the most driven, energetic, and compelling young founders in today’s chip industry,” Boland said in the company’s press release. “His conviction that Tattvam AI will dramatically speed up the complex and iterative process of using EDA tools and models to design chips, cutting timelines from years to weeks, is sure to be embraced by the world’s top teams.”
You’d expect this in the official company announcement, but Daniel Dippold echoed this. “Bragadeesh is one of those rare founders who reasons from atoms up: He turned down Google’s TPU team because he’d rather build the infrastructure that makes the next decade of compute possible,” Dippold said. “When we met him, he’d already shipped across brain-computer interfaces, 5G, and AI silicon. We see thousands of founders a year at EWOR. Very few of them make you feel like the market is simply going to bend around them. He’s one of those.”
The company currently consists of Bragadeesh and his co-founder, Lannan Jiang, who previously worked on high-performance chip development at ETH Zürich. However, Bragadeesh told EE Times that Tattvam AI is hiring and expects to have five people working full time on this mission by the end of 2026.
Following the end of our chat, we asked what the meaning was behind the company name, Tattvam AI. Bragadeesh told EE Times, “My interpretation of the word Tattvam is that it means the ‘fundamental principle of things.’ The company’s origin was based on the intuition that if you can build an AI model that understands the structure of the problem you’re solving from first principles, there’s a wide variety of applications. For example, Harmonic is applying similar thinking in AI for math. We’d like to bring a similar approach to chip design, which is essentially a collection of puzzles. We’re building an AI that can reason through the structure of the circuit from first principles and solve physical design puzzles.”
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