IBM, Lam Research Focus High-NA EUV on Sub-1-nm Nodes

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IBM and Lam Research aim to make chips beyond the 1-nm node. The companies, however, declined to disclose potential chipmaking partners or a timeline for commercial production.

IBM and Lam Research have a five-year agreement focused on developing new materials, fabrication processes, and High-NA EUV lithography to advance IBM’s logic scaling roadmap, the companies said in a March 10th news release. In 2021, IBM became the world’s first to make a 2-nm chip, and later partnered with Japan’s Rapidus to manufacture 2-nm devices by next year.

IBM and Lam Research aim to develop High-NA EUV lithography processes for new interconnect and device patterning, thereby accelerating industry adoption of ASML’s most advanced lithography tool. Foundries like industry leader TSMC haven’t adopted High-NA EUV yet and instead continue to use multi-patterning workarounds that extend the use of Low-NA EUV patterning tools.

“We are thrilled to be expanding our collaboration to tackle the next set of challenges to enable High-NA EUV lithography and sub-1-nm nodes,” Mukesh Khare, general manager of IBM Semiconductors at IBM Research, stated in the press release.

In the new era of 3D scaling, progress relies on materials, processes, and lithography that come together as a single, high-density system, said Vahid Vahedi, chief technology and sustainability officer at Lam Research.

“We are proud to build on our successful collaboration with IBM to drive High-NA EUV dry resist and process breakthroughs, accelerating the development of lower-power and higher-performance transistors that will be critical for the AI era,” Vahedi stated.

IBM earlier this year said it aims for sub-2 nm nodes with heat-modeling technology it developed with Synopsys and the support of U.S. military research agency DARPA. The companies told EE Times they will share the technology with chipmaking partners as the 2-nm node ramps up. TSMC and other chipmakers, such as Samsung, started industry-leading 2-nm node manufacturing last year.

Stumbling block

The 2-nm node that’s critical for the advance of AI has been a stumbling block for some of the world’s leading chipmakers, including Samsung and Intel. TSMC dominates the most advanced node that’s in commercial production, and the company has done it without adopting High-NA EUV.

Defining a decade

IBM expects High-NA EUV to define the next decade of chip scaling.

“IBM believes accelerating its adoption will unlock the high-performance AI chips needed for the AI era,” Khare told EE Times. “However, reaching that point will require advances in materials, etch and deposition processes, pattern transfer, and more to capture the cost and performance benefits.”

As logic devices move toward sub-1 nm, pattern transfer and defectivity have become fundamental barriers, Vahedi told EE Times.

“Device dimensions push the limits of physics, requiring entirely new materials, patterning techniques, and atomic-level process control strategies,” Vahedi said. “Yield is increasingly driven by atomic-scale fluctuations and process interactions. This makes co-optimized, atomic-scale deposition and etch flows a key challenge for sub-1-nm logic. Lam will focus on enabling atomic‑level precision in patterning, etch, and deposition so that ultra-fine EUV patterns can be reliably transferred into real device layers with production‑level yield.”

Scaling to advanced nodes increasingly requires tighter pitches than can be achieved with Low-NA single patterning, Lam said.

“In Low-NA, these advanced nodes require multiple patterning, which results in higher cost, longer cycle times, and lower yield,” Vahedi said.

Lam Research’s latest dry-resist and patterning technologies improve resolution and defectivity, enabling direct-print High-NA EUV patterning—giving chipmakers improved yield with better patterning resolution, he added.

IBM’s chip legacy

After exiting the chip manufacturing business decades ago, IBM has continued to develop semiconductor technology at the Albany NanoTech Complex in the state of New York. The New York facility hosts the first public-private High-NA EUV lithography center in North America. In addition to its work with Rapidus at Albany NanoTech, IBM has a foundry partnership with Samsung.

In this latest semiconductor partnership with Lam Research, “our teams aim to develop full process flows for nanosheet and nanostack devices and backside power delivery,” Khare said. “The goal is to enable reliable transfer of High-NA EUV patterns into device layers with high yield and support continued scaling, improved performance, and viable paths to production for future logic devices.”

See also:

Lam Research, CEA-Leti Open Fast Lane for Specialty Technologies

IBM, Synopsys Move Toward 1.4-nm Node With Heat-Modeling Tech