Why chiplets and why now? A special section at EDN provides a detailed treatment of this revolutionary silicon technology that’s transforming the semiconductor industry at a time when AI is forcing every serious silicon team to modularize, mix-and-match, and move faster.
This special section will chart key building blocks of chiplet technology—3D ICs, advanced packaging, compute subsystems, heterogeneous integration, interconnects, memory wall, and more—while separating hype from reality.
Find out how system-on-chip (SoC) designs differ from multi-die systems and how standards are evolving in the multi-die chiplets world. Next, a senior executive from a chiplet startup shares how it’s advancing AI systems with HBM4- and SPHBM4-based DRAM solutions.
A technical piece takes a closer look at the chiplet-based design flow and the sequence of tasks, which appears nearly identical to that of a monolithic system-on-chip (SoC) design on the surface. Though in reality, chiplet designs significantly diverge from most SoC designs.
Another article will outline eight best practices for multi-die designs, given that these designs introduce new engineering complexities in areas such as packaging, verification, and thermal dynamics. For instance, it will show how designers can treat packaging as part of the design and engineer the interconnect like a subsystem.
Another article presents 3D ICs as a practical framework for heterogeneous integration. After listing the unique challenges of advanced packaging, it offers tips for efficient 3D IC design and an expert guide to heterogeneous integration.
Then there is a blog taking a sneak peek at co-packaged optics (CPO) challenges and how advances in photonics are aiming to overcome them, including signal integrity, thermal management, optical alignment, and cost. CPO offers a vital alternative to semiconductor packaging built around copper interconnects.
Stay tuned for this chiplets design summit, one article at a time.
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