MOSIS 2.0 Developer Workshop to Showcase Advanced Semiconductor Prototyping & IC Design at IMS 2026


MOSIS 2.0 Developer Workshop to Showcase Advanced Semiconductor Prototyping & IC Design at IMS 2026

MOSIS 2.0, a USC-led semiconductor prototyping initiative/ecosystem, will host its MOSIS 2.0 Developer Workshop during IMS 2026 in Boston, highlighting semiconductor prototyping, fabrication access, advanced packaging, and IC design support for the RF and semiconductor development community.

The workshop will take place on Wednesday, June 10, 2026, from 12:00 PM to 2:00 PM at the Thomas M. Menino Convention & Exhibition Center (MCEC), Room 108. The session will focus on how MOSIS 2.0 enables accelerated semiconductor prototyping through access to advanced research laboratories, semiconductor foundries, multi-project wafer (MPW) programs, and engineering support resources.

Semiconductor Foundry and Fabrication Access

One of the key topics at the workshop will cover access to both advanced and legacy silicon CMOS technologies through leading semiconductor foundries including GlobalFoundries, Intel, SkyWater Technology, Samsung Electronics, and TSMC. The workshop will also address compound semiconductor technologies, including GaN HEMT, InP HBT, and InP photonic integrated circuit (PIC) platforms, supporting RF, microwave, photonics, and high-frequency device development.

Advanced Packaging and Integration Technologies

MOSIS 2.0 will showcase capabilities related to advanced semiconductor packaging and heterogeneous integration. Topics will include assembly techniques such as wire bonding, flip-chip integration, wafer-level bumping, sub-dicing, and interposer-based solutions designed for advanced RF and mixed-signal system integration. The workshop will additionally highlight custom split-fab semiconductor fabrication capabilities available through university and low-volume manufacturing facilities, supporting specialized research and prototype development requirements.

Rapid Prototyping and IC Design Support

Another focus area will be the MOSIS Advanced Prototyping Platform (MAPP), designed to support rapid FPGA-to-ASIC testing and accelerated hardware validation workflows. The company will also discuss its IC design services and engineering support capabilities available to developers and research teams.

During the workshop, MOSIS 2.0 will also announce the award recipients for the HRL T3L GaN MPW Access Program.

In addition to the workshop sessions, attendees will be able to meet the MOSIS 2.0 team at booth 24084 during the IMS 2026 exhibition. 

Click here to register for the MOSIS 2.0 Developer Workshop at IMS 2026.

Click here to learn more about MOSIS 2.0 semiconductor services.



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