Memory customization is not always a top priority when a design team plans a new system-on-chip (SoC) project. But often it should be.
This may not be an obvious statement. Granted, SRAM claims a lot of area on most SoCs. The speed and power consumption of SRAM arrays can affect the overall chip performance and energy efficiency.
But today’s memory compilers are flexible tools that support a variety of cell designs. At Faraday, for example, the 14FFC compiler offers eight variants, tuned to diverse needs, ranging from high-density to high-performance to ultra-low-power. So why do you consider custom memory?
One answer to the above question is the need for an unusual word or bit length. Relatively simple customization can produce the exact SRAM configuration required for a specific instance, not just the compiler’s closest approximation.
Similarly, there are times during floorplanning—or, more concerningly, during timing closure—when giving an SRAM instance an unusual aspect ratio can ease a difficult situation. This may be a more complex customization, requiring changes to array layout and routing, multiplexers, drivers, and cell designs.
Recently, we designed a multi-Mbit SRAM array with an aspect ratio of nearly 1:19. This memory architecture is ideally suited for seamless integration into frame-buffer applications specifically designed for display processing. The memory configuration, characterized by its unique aspect ratio, is carefully engineered to accommodate wide I/O widths and specialized non-2n-column multiplexing requirements.
Figure 1 Special aspect ratio memory in this case is x = 1775 um, y = 95 um; giving an SRAM instance an unusual aspect ratio can ease a difficult situation. Source: Faraday Technology
Another situation involves yield and reliability. Compilers typically only generate a specific number of redundant columns of bit cells. In the event of a bit failure, the array can disconnect the offending cell’s column and replace it with a redundant column if one is available. This technique is effective if failures only occur in one or a few columns.
But for various reasons, some designs require more protection: redundant columns and redundant rows. The additional cells, routing, and logic to implement this expanded redundancy can be achieved by customizing the array.
Figure 2 This memory offers redundant rows and columns for additional rows and columns. Source: Faraday Technology
An automotive case study
Another example of memory customization comes from a recent SoC design we participated in. The project was for a mission-critical automotive SoC. Our customer specified an Automotive Grade 1 (AG1) operating ambient temperature range of -40 to +125 °C.
Within that range, the customer required an extended operating life, as is customary for automotive electronics. And the chip would require ISO 26262 functional safety certification, which would require enhanced failure analysis and documentation during design.
This project illustrates the level of detail sometimes needed in memory customization. But it also shows the extent of additional support—analysis, documentation, design assistance, and test services—that a custom memory design can entail.
We determined that existing tools could produce an array that would operate reliably over the AG1 temperature range in the short term. But to achieve the required operating life, we had to address aging issues in the circuitry.
First, there was the issue of high-current signals on the array’s word lines and bit lines. The customer was rightly concerned that, over the operating life and at elevated temperatures, the high currents could cause sufficient electromigration to trigger chip failure. So, we redesigned the line drivers and the array, preserving array performance, signal integrity, and line-direction management while reducing the risk of electromigration.
Bias temperature instability (BTI) was another threat to chip life: time and elevated temperature cause a gradual but significant drift in MOSFET threshold voltages. Unfortunately, NMOS and PMOS devices age differently under BTI. So very gradually, the timing of rising and falling signal edges can diverge. Eventually, this can lead to circuit failure at points where the relative arrival times of two signals, one positive-going and one negative-going, are critical. Accordingly, we altered the memory design.
We further inspected the remaining control logic for the risk of developing race conditions over time and adjusted timing margins to account for eventual threshold-voltage drift. The result was a significant improvement in SRAM’s expected operating life.
Functional safety
Certification under ISO 26262 was another requirement. This comprehensive standard delves deep into the design process to ensure that chip failure modes are identified, traced to their root causes, and addressed. This process extends to IP used in the design and to the original circuitry. So, the documentation required for ISO 26262 certification was deliverable for the custom memory team.
Two primary documents are required: a Design Failure Mode and Effects Analysis (DFMEA) and a safety manual. The former, as its name suggests, is an exhaustive list of the ways the IP could cause an error, the possible causes of those failure modes, and the remedial actions taken. The safety manual, in contrast, is an instruction manual for the chip and system designers who will integrate the IP into the overall design.
One entry in the DFMEA might include a failure in which a bit cell flips, corrupting data in the SRAM. Under this heading, list potential causes of a flipped bit, including design-rule violations in the cell array, radiation upset, and aging. For each reason, there would be a list of controls to prevent it or detect it, an assessment of the remaining failure risk, and recommendations for further action.
The safety manual tells IP integrators and system developers how to use the IP without violating the conditions for which it was designed. Directions might include, for instance, input signal and supply voltage ranges, noise limits, substrate noise and temperature limits, output loading specifications, and maximum duty cycle limits.
Why custom memory design?
As these examples illustrate, custom memory design can adapt an array exactly to functional, timing, or layout requirements of a particular SoC. It can also produce arrays for demanding performance, environmental, or reliability requirements.
But seeing a customer through to a finished SoC requires far more than just providing the design files for a custom SRAM array. The design partner should be ready to assist the SoC design team with integration, provide verification and test support, and thoroughly document the characteristics and requirements of the new SRAM design.
In addition, the partner should be able to work intimately with the SoC foundry to ensure yield, and with the test vendor to ensure adequate test coverage for the new array. In many cases, it’s an advantage for the partner to have in-house testing capability.
Roger Chen is deputy division manager for memory IP development at Faraday Technology.
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