Circuits for converting 4 to 20mA analog current loop signals to 0 to 20mA may be hot topics, but hot implementations of those circuits are not.
Circuit designs for conversion of 4 to 20mA analog current loop signals, which are ubiquitous in process monitoring and control, to 0 to 20mA are a hot topic recently. “Hot topic” is a perfect description because typical examples of such converters can dissipate half a Watt. Some cook even hotter than that! This results in some very un-green complications like TO220 packaged power pass transistors sporting substantial heatsinks. Would Greta T. approve? I think not!
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The design in Figure 1 offers a cool (and maybe even useful) efficiency improvement. It thriftily recycles most of the 4 to 20mA input current to generate the 0 to 20mA output while needing only microamps from its own local power supply. It consumes merely 250uA x 24v = 6mW (typical) and dumps only similar single-digit milliwatts from Q2 (which is the closest thing it has to a pass transistor). That’s not even enough heat to make a TO92 tepid.
Here’s how it works:
Figure 1 This circuit’s operation is governed by the following equation: Iout = Iin – 4mA(1 – (Iin – 4mA)/16mA)) = 1.25(Iin – 4mA). The maximum current drawn from the local V+ supply is only 1/80th of max Iout, translating to an 80:1 efficiency gain. Asterisked resistors are 0.5% precision or better.
The 4 to 20mA input current (99.95% of it, to be precise) passes through current sense resistor R1 and from there to the load, generating 200mv to 1v as Iin goes from 4 to 20mA. The voltage to current converter R1+A1+Q1 makes that into Ic1 = Iin R1/R2 = 2uA to 10uA as the input to current to voltage converter R5+A2+Q2+R4, generating 0.5 to 2.5v across R5. A2 compares this to A3’s 2.50v internal reference, forcing Q2 to conduct so that the sum Vr4 + Vr5 = 2.5v.
Thus Ic2 = (2.5 – Vr5)/R4 and it decreases linearly from 4mA to zero as Iin increases from 4 to 20mA. The net effect is to force Q2 to subtract a linearly decreasing 4 to 0mA from Iin, so that its 4 to 16mA span is corrected to 0 to 20mA in Iout. In other (mathspeak) words: Iout = Iin – 4mA(1 – (Iin – 4mA)/16mA)) = 1.25(Iin – 4mA)
The payoff is that 98.8% of Iout comes from recycled Iin instead being sucked anew from V+.
V+ isn’t critical and needs only be sufficient to provide the compliance required by the (grounded) load. R3 needs to provide 50uA bias for the A3pin3 shunt reference, so R3 = (V+ – 2.5)/50uA = 390k for V+ = 24v. Noncritical Z1 provides a few volts of headroom for the transistors. The total voltage drop from input to output is 5.6v.
Finally, there’s a caveat. In the event of complete loss of the nominal 4 to 20mA input current, A2 will drive Q2 into saturation. This won’t damage anything, but will force A2 to draw 5mA from V+ to supply the required Q2 base current.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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