Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?

Apple Silicon’s success track record is indisputably impressive. It’s also rife with implementation inconsistency, albeit reflective in no small part of broader industry status impermanence.

When Apple announced its computing platform migration from Intel x86 to homegrown Arm-based SoCs beginning in mid-2020, initial industry response was initially mixed. There was no shortage of schadenfreude, mind you, both considering that Intel had done the same thing to the IBM/Motorola PowerPC Alliance a decade and a half earlier, and more broadly Intel’s then-status as the predominant processor supplier to the computing segment. That said, and as was hopefully evident even in my earliest Apple Silicon era coverage, I was personally confident in the strategy’s sooner-or-later transition success, which is ironically winding up as we speak.

For one thing, Apple’s relationship with Intel was growing increasingly strained, as the chip supplier’s power consumption vs performance trends grew more worrisome, as new-product schedules slipped, and as the bugs in those products multiplied. For another, Apple and foundry partner TSMC (superseding initial partner Samsung) had for a while already been developing new SoCs for smartphones, tablets, smart watches and other devices. And then there’s Apple’s in-house vertical integration and control of both hardware and software, the latter spanning both operating systems and first-party applications and suites, as well as its exclusivity as provider of both developer tools and App Store approvals for third-party coders.

New life

And so here we are with today’s M6, the company’s latest mainstream SoC offering. It’s notable for being the premiere volume production implementation of TSMC’s newest 2 nm fabrication technology foundation. And Apple’s done (as well as, equally notably, not done) numerous things, most of them predictable but a few more surprising, with the expanded (albeit more expensive) transistor budget it’s been foundry-afforded.

The M5, introduced last October, integrated 10 (max, “binned” to fewer than this in some product proliferations to maximize yield and minimize cost) CPU cores and the same 10 (again, max, and again, binned in some variants) GPU cores. Each GPU core also integrated a Neural Accelerator, a fancy name for what’s likely “just” (I jest) a general-purpose massively SIMD revamp of the graphics architecture for enhanced function flexibility. And then there was the standalone 16-core Neural Engine for optimal, albeit function-specific, inference processing.

And the M6? 12 (max, bin-dependent) CPU cores this time: two “super”, four “performance” and six “efficiency”. Clock speeds, no surprise, aren’t public, nor are cache sizes or other important-to-engineer characteristics. 12 (max, again) GPU cores this time, too. And two 16-core Neural Engines. The AI emphasis is obvious, yes? And what about performance? Apple claims “up to 1.2x faster multithreaded performance as compared to M5,” which is to some degree to be expected due to the greater CPU core count, although more than a straight linear interpolation would be expected to deliver. And single-threaded improvements? I thought you’d never ask…and some part of me wishes you wouldn’t have asked, because the answer is so very lame. “It delivers the world’s fastest single-threaded performance.” That’s it. Seriously, Apple?

Life extension

What about the M5 family; is it drifting off the stage as the M6-series successors take their turn in the spotlight? Not quite…and maybe not for a while yet (hold that thought). Apple just introduced the M5 Ultra SoC, combining two M5 Max die via a silicon interposer “stitching” technology the company brands as UltraFusion. Here’s the twist…the M5 Max itself, as I wrote about in March, is a dual-die UltraFusion-stitched configuration, as is its M5 Pro enabled-core-count subset. So, what we have here is Apple’s first quad-die, UltraFusion-combined design.

This all leads back to the “implementation inconsistency” allusion in the upfront subhead of this writeup. The first-generation Apple Silicon M1 family die shots are shown at the beginning of this section. The M1, along with the M1 Pro and M1 Max, were all single-die designs, albeit (as you can see if you look closely) with the die area devoted to the M1 Max’s graphics subsystem effectively implemented as a mirror-image doubling of that in the M1 Pro. But the M1 Ultra, unveiled ~1.5 years after the M1, employed UltraFusion dual-die merge for the first time.

Apple has skipped the “Ultra” tier for both the M2 and M4 generations; this is the first time we’ve seen one since the M3 series, where the baseline, Pro and Max tiers were simultaneously unveiled, all in single-die form, and with the M3 Ultra once again arriving 1.5 years later as a dual-die stitched design. This time around we’ve got, adding together the innate resources of each of the four dice, an up-to-36-core CPU consisting of 12 super cores and 24 performance cores, and a next-generation GPU as many as 80 cores. Compared to the M3 Ultra, Apple claims that the M5 Ultra’s CPU subsystem delivers up to 1.25x higher single-threaded performance and up to 1.3x higher multithreaded performance, with the GPU cluster supplying up to 4.5x the peak GPU compute for AI. Note, again, the AI emphasis, as if it was even possible to miss!.

Price explosion

The first systems containing these new chips are, for the M6 (and already introduced, but first-time in this form factor, M5 Pro), the Mac mini.

And for the M5 Ultra (and already introduced, but first-time in this form factor, M5 Max), the Mac Studio.

The key aspect of these parts of the story is, unsurprisingly, memory—DRAM for system and unified graphics and flash memory for the SSD—and their impacts on pricing versus with prior-generation systems in less supply-constrained times. The case study example in one of John Gruber’s event coverage posts tells, I think, the tale best of all.

If you configure an M6 Mac Mini with 2 TB of storage, the SSD upgrade ($1,000) costs more than the entire base model computer ($900). So too with the 4 TB SSD upgrade for the M5 Pro Mini ($1,800 upgrade for a $1,700 computer).

I’ll also posit a question: why did Apple make this announcement now, particularly given that initial system configurations won’t start shipping until late next month, with higher-end follow-on tiers not available until (at least) October? The company is widely expected to roll out its next-generation iPhones (high-end variants, at least), smart watches, earbuds and other related (and not?) goodies in just two weeks’ time; why not just unveil everything all at once?

Mebbe Apple’s already got so much already planned for September 9 (I’m guessing) that it decided to split the total tranche into two events out of necessity? Or maybe Intel…or AMD…or Qualcomm…or Nvidia…or some other chip and/or system supplier has something already planned for the near future, and Apple caught wind of it and decided to launch earlier than originally planned (note the lack of a dedicated event today) to steal competitive thunder?

What’s next?

I saved the best for last, IMHO and if the rumors are true. Using past history as a (potential) guide to the future, when will Apple roll out the M6 Pro, Max and maybe even Ultra (though, as already noted, this only seems to happen in odd-number generations) SoCs? How about never?

For many years, although it admittedly still boggles my mind to type these words, we’ve largely in-retrospect learned that Apple apparently was seriously involved in the development of an Apple-branded, battery-powered and autonomous car. The project is now mothballed, with the former test track now owned by Waymo, although its lineage lives on somewhat in Ferrari’s Luce, designed in conjunction with former Apple chief design officer Jony Ive and shown above.

The Apple Car project apparently involved not only vehicle hardware and software development but also dedicated-silicon development, specifically for inference processing. Apple is reportedly now “baking” its inference learnings from those earlier efforts into an accelerated development timeframe for its M7-series (and beyond) SoCs. As such, to the “stutter step” reference in the title, there supposedly won’t be any M6 variants, therefore systems based on them, beyond the baseline chip introduced today (and also encompassing, I’m guessing, pending updates to the 24″ iMac and the MacBook Air).

I’ve long believed, and intend delve into further detail in a near-future dedicated-topic blog post to come, that the long-term winners in AI silicon will be:

Volatile and nonvolatile memory suppliers, and
Dedicated-function inference processor and core suppliers

for the same fundamental reason: inference processing largely done today in the “cloud” will inevitably move, at least in part, to the edge. And what better case study for the trend exists than an autonomous vehicle, which absolutely cannot tolerate the lengthy roundtrip processing latency from the vehicle to the cloud and back, assuming it even has reliable connectivity at all?

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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