Power Tips #156: How to design a high-boost-ratio boost converter

The maximum boost ratio achievable with a single stage, normally cited as 8-to-9, can be much higher if you keep important design considerations in mind.

In single-cell battery applications such as personal electronics or power tools, where the input voltage is less than 4V, you may need a high output voltage to reduce current in the system in order to provide higher power density, faster charging, improved efficiency and a small form factor. High-boost-factor designs allow a high ratio between the input and output voltage. This article discusses the process for designing a high-duty-cycle boost topology suitable for high-output-voltage applications, while showing the limits of achievable duty cycles and boost factors.

As a rule of thumb, the maximum boost ratio practically achievable with a single boost stage using regular silicon switches is often cited as 8-to-9. Much higher ratios are still possible, however, if you keep important design considerations in mind.

High-duty-cycle considerations

A boost converter can operate in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In DCM, the inductor current reaches zero every switching cycle, whereas in CCM current always flows through the inductor. When operating in DCM, a combination of small inductance, low output current and low switching frequencies helps achieve a high boost ratio, as expressed by Equation 1.

$V_{out\_DCM} = V_{IN} + \frac{D^{2}_{DCM} \times V^{2}_{in} \times T_{S}}{I_{out} \times 2 \times L}\text{ (1)}$

Achieving a high boost ratio in CCM requires a high duty cycle, as shown by Equation 2.

$V_{out\_CCM} = \frac{V_{in}}{(1-D)}\text{ (2)}$

While in theory a duty cycle of 99.9% (and a boost factor of 1,000) is possible, practical limitations exist. Most boost controller or converter integrated circuits have a maximum duty cycle dependent on switching frequency – typically in the range of 92% to 98%. Gate charge and other parasitics of the field-effect transistors (FETs) and printed circuit board traces limit the maximum duty cycle. Additionally, the higher the duty cycle, the lower the right-half-plane zero frequency becomes, which can result in a very slow regulation loop.

Choosing the switching frequency

Selecting a switching frequency involves a trade-off between efficiency and solution size. For a high boost ratio, a lower switching frequency is preferable. When designing for DCM, the frequency must be low enough to maintain DCM operation for a given inductance value. Thus, a lower switching frequency directly helps achieve a higher boost factor in DCM.

In CCM, the switching frequency theoretically does not influence the maximum boost factor, but drive strength and metal-oxide semiconductor field-effect transistor (MOSFET) turnon and turnoff time will limit it in practice. If the driver is weak and the MOSFET switching speed is low, a lower switching frequency is better.

Choosing the inductor

As a rule of thumb, in CCM, an inductor current ripple between 15% and 40% of the maximum load current is preferable. A higher inductance value tends to increase peak efficiency, while a lower inductance value can achieve higher full-load efficiency.

For high boost ratios in CCM, the inductance may need to be high enough so that the internal slope compensation ramp is sufficient. As shown by Equation 3, the slope compensation ramp needs to be at least half of the sensed inductor current’s falling slope.

$S_e = \geq \frac{1}{2}S_f = \frac{1}{2}( \frac{V_{out}-V_{in}}{L} \times R_{sense})\text{ (3)}$

For a DCM design, the inductance needs to be small enough to operate in DCM at a full load for the given frequency. This can result in high peak currents. Operating in DCM is advantageous because it allows you to achieve a higher boost ratio. Typically, the inductor DC resistance (DCR) must remain small, since DCR has a strong effect on achievable performance.

Component-level design considerations

For the MOSFET, the drain-to-source on-resistance (R_DS(on)) must be small, since it has a strong influence on the achievable boost factor. Gate-drain (Qgd) and gate-source (Qgs) charges directly affect the rise and fall time of the switch, respectively, and become a limiting factor for achieving a high boost factor when the driver is weak or the switching frequency is too high.

The total gate charge (Qgate) compounds this issue further, demanding a stronger driver simply to keep switching losses and timing under control. The FET output capacitance, Coss, has a small impact on the maximum achievable boost factor, as long as it does not limit the duty cycle to a lower value than necessary.

This is precisely where gallium nitride (GaN) FETs offer a decisive advantage over silicon MOSFETs: their substantially lower Coss, Qgd, Qgs and Qgate enable much faster switching without requiring an oversized driver, removing this bottleneck and unlocking higher achievable boost ratios.

The output diode in synchronous designs does not significantly influence the boost factor, since its voltage drop occurs on the output side of the converter. A synchronous or nonsynchronous topology also has low impact in this regard.

Finally, both the output capacitor and input capacitor have low impact on the boost factor; for the input capacitor, this holds true as long as the input source is strong, meaning that it has low impedance.

High-boost-ratio design example

Figure 1 shows a single-cell, 3V-to-42V boost converter using the LMG5126 integrated GaN boost converter from Texas Instruments (TI).

Figure 1 The TI 3V to 42V Synchronous GaN Boost Converter Reference Design uses the LMG5126 boost converter with integrated GaN FETs. Source: Texas Instruments

This design achieves an ultra-high-boost ratio of 14-to-1 while delivering up to 20W of output power and maintaining efficiency over 84%, as shown in Figure 2.

Figure 2 GaN FETs ensure over 84% efficiency at 600kHz. Source: Texas Instruments

To avoid the high peak currents associated with DCM operation, the converter operates in CCM, requiring a duty cycle of 93%. A 600kHz switching frequency minimizes the overall solution size. Figure 3 shows the resulting high-duty-cycle switch-node voltage.

Figure 3 This graph shows the LMG5126 boost converter’s switch-node voltage for V_IN = 3V. Source: Texas Instruments

Conclusion

Inductor DCR and MOSFET R_DS(on) have a high impact on achievable boost factor and should be priorities during component selection. FET rise and fall time may limit the maximum boost factor, and are closely tied to driver strength, gate resistor and FET parasitics. GaN FETs can help enable higher switching frequencies and will increase the boost factor.

Finally, it is essential to check the controller’s maximum duty cycle rating, since this may depend on switching frequency or other design parameters. Following these tips will help ensure success on your next high-boost-ratio converter design.

Florian Mueller is a systems engineer and Member Group Technical Staff in TI’s Power Supply Design Services group. He has a master’s degree in electrical engineering from the Technical University of Haag, Germany. Florian’s main focus lies on industrial high-voltage designs for different end equipment.

Moritz Mueller is an applications engineer at Texas Instruments. He has a master’s degree in electrical engineering from the University of Applied Sciences in Landshut, and mainly works on synchronous and nonsynchronous boost converter and flyback designs.

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