Significantly simpler square wave circuits for frequency division by even numbers

An AND gate replaces comparators to cut a frequency divider’s chip count.

In his recent Design Idea, “Frequency division by any even number, with a 50% duty cycle output,” frequent contributor Jayapal Ramalingam presents a nice family of frequency divider circuits with symmetrical square wave outputs.

The circuit designs shown there share a topology. It comprises a ripple-carry counter, a comparator that generates a reset pulse when the counter reaches a terminal count equal to half the chosen division ratio, and a final divide-by-two square wave-generating output flip-flop. Two examples of this basic topology are shown in the Design Idea. One implements division by 10 and consists of three chips. Another divides by 48 and requires four chips.

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There’s certainly nothing functionally wrong with these clever designs. They work. However, I noticed an opportunity for a significant simplification and reduced parts count that arises from a familial property of ripple carry counters.

They ripple.

When a clock pulse increments the contents of such counters, zeros propagate (ripple) through the stages until ending by hitting and flipping a zero bit to a one. Consequently, detection of the chosen terminal count doesn’t require an actual comparator, but can be done with a simple AND gate. This is shown in Figure 1’s two-chip solution to the frequency-division problem.

Figure 1 This divide-by-10 circuit utilizes U2a’s AND gate to decode U1a’s ripple carry counter to get a divide by 1 + 4 = 5. This is cascaded with U2b’s division by 2 for Fout = (Fin/5)/2 = Fin/10 = a 50:50 square wave.

Here’s how it works.

Four-bit ripple counter U1a combines with 4-input AND gate U2a to create the desired division ratio. The ratio created is equal to the sum of the U1a output weights that are connected to U2. Ratios from 1 through 15 are therefore available. Figure 1’s example shows 1 + 4 = 5.

When U1a ripples up to the chosen ratio, U2a pin 6 goes to a logic “1” which resets U1a to back to zero and advances U1b by one count, toggling its least significant bit (LSB) output. U1b thus performs an additional power-of-2 division which can be any of 4 possible ratios: 2, 4, 8, or 16. Figure 1’s example of this illustrates a net division of 5 x 2 = 10.

But of course, a total of 15 x 4 = 60 possible ratios exist. Any ratio can be chosen from the sequence 2, 4, 6, … 30, 4, 8, 12, … ,60, 8, 16, 48, …, 120, 16, …, 240.

Figure 2 shows how this same concept works for a division ratio of 48, while still requiring just two chips.

Figure 2 In this divide-by-48 example, U2a decodes U1a to divide by 4+8=12, followed by U1b’s division by four for Fout = (Fin/12)/4 = Fin/48.

And Figure 3 shows division by 100, still with a 50:50 output and still implemented by just two chips.

Figure 3 In this divide-by-100 example, U1a divides by 16, then U2a decodes 1+8=9 for 16+9 = 25, followed by U1b’s division by four for Fout = (Fin/25)/4 = Fin/100.

If you build one, don’t forget to tie U2’s unused inputs to V+ or ground.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.

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