The pages of Design Ideas (DIs) have recently been awash in a veritable cascade of designs for variable frequency oscillators with frequency ranges tunable over multiple decades:
But despite the size of this crowd, a notable feature missing from all is provision for digital control (e.g., from an MCU GPIO pin) of the oscillation frequency. This DI will address that topic.
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When starting the design of any digital to analog interface, the first question to be answered is how much resolution (bits) do we need? For the applications listed above, the answer isn’t obvious. That’s because of the extremely wide range of the analog quantity (frequency) involved, e.g., 100,000:1 for Christopher Paul’s 5-decade 10 Hz to 1 MHz sawtooth generator.
5 decimal decades = 10ppm and is equivalent to a linear binary resolution of 16.6 bits. So even if we went with the overkill choice of 16bits (1/65536 = 15ppm), we’d still lose resolution at the bottom end. The first least significant bit (lsbit) increment up from 10 Hz would comprise a 15 ppm of 1 MHz = 15 Hz jump to 25 Hz, nearly trebling the output frequency.
Figure 1’s circuit takes an approach very different from linear conversion. Working from mere 8bit PWM, it makes lsbit incremental resolution constant and uniformly distributed at ~5% of output. Here’s how it works.
Figure 1 Antilogarithmic 8-bit PWM gives s constant incremental ~5% per lsbit. Asterisked parts are 1% or better precision (metal film or C0G).
Antilog conversion occurs in a four step ~1ms cycle defined by the combined states of the GPIO PWM bit and D flip/flop decoded by the 4052 analog switch as shown in Figure 2.
Figure 2 Tw = antilog RtCt timeout = 1 to 250 counts = 2 to 500 µs, where
PWM = 1 + 21.63*Ln(Imax/Iout)
The antilog conversion sequence is as follows:
- BA = 3. duration 12 µs. Timing capacitor Ct charged to Vdd – 1.24 V.
- BA = 2. duration Tw = 2 µs to 500 µs. Ct exponentially discharged toward Vdd with time-constant RtCt = 43.4 µs.
- BA = 1: duration 0 to 498 µs. Ct residual charge transferred to Csh sample and hold cap.
- BA = 0: duration 2 µs to 500 µs. Ct residual charge continues to transfer to Csh.
At the end of each 4-step, 1024-µs cycle, Csh will converge toward a charge relative to Vdd between 12 µV and 1.2 V, determined by the antilog of the 2 µs to 500 µs duration of phase 2 of the conversion sequence. The 1-µV typical input offset of the LT2066 makes this adequate for (reasonably) accurate digital to analog conversion. Convergence of Vcsh to 8-bit precision takes a maximum of 8 cycles = 8.2 ms.
Final conversion of the resulting 5-decade current source to a 5-decade frequency output (the point of the exercise) can be done simply (if admittedly kind of crudely) with the circuit in Figure 3.
Figure 3 A minimal 5-decade sawtooth oscillator that enables final conversion of the resulting 5-decade current source to a 5-decade frequency output.
Or it can be done much more precisely with Christopher Paul’s DI by substituting Figure 1 for his original resistor-programmed current source (highlighted in yellow), as shown in Figure 4.
Figure 4 Maximal 5-decade sawtooth oscillator, using Christopher Paul’s DI.
Figure 5 Log (red) and linear (black) plot of source current versus PWM.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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