Part 1 of this article series on gallium nitride (GaN) fundamentals described crystal structures and the formation of the two-dimensional electron gas (2DEG), along with material figures of merit and the transition from depletion-mode to enhancement-mode GaN HEMTs.
Part 2 will outline hybrid structures and the RDS(on) penalty, as well as provide further details on GaN HEMTs and substrate choices for GaN. It will also make the case for the path to monolithic integration while showing how ohmic contacts, metallization, and packaging advantages are facilitating this design roadmap.
Figure 1 Schematic of low-voltage enhancement-mode silicon MOSFET is shown in series with a depletion-mode GaN HEMT: Cascode circuit (a) and enable/direct-drive circuit (b). Source: Efficient Power Conversion (EPC)
An alternative to monolithic enhancement-mode GaN transistors is the hybrid cascode configuration, pairing a low-voltage enhancement-mode silicon MOSFET with a high-voltage depletion-mode GaN HEMT in series. Figure 1 above illustrates two variants.
The cascode configuration, in particular, is highlighted as a pragmatic intermediate solution: a low-voltage enhancement-mode Si MOSFET is connected in series with a high-voltage d-mode GaN HEMT. The MOSFET gate is the external control terminal; when it turns on, the GaN gate-source is pulled close to zero and the HEMT conducts. When the MOSFET turns off, the GaN gate sees a negative bias through the MOSFET, turning off the high electron mobility transistor (HEMT) and providing normally-off behavior at the system level.
A natural question is how much extra RDS(on) the silicon MOSFET adds to the GaN device. Figure 2 shows a useful plot of the percentage contribution of the MOSFET to total RDS(on) versus the rated voltage of the cascode system. At high voltage, the GaN device dominates, and the MOSFET contribution becomes small.
Figure 2 Percentage RDS(on) contribution from the low-voltage MOSFET in a cascode configuration is shown as a function of the rated breakdown voltage of the composite device. Source: Efficient Power Conversion (EPC)
From this chart, a 600-V cascode device adds only around 3% extra RDS(on) due to the low-voltage MOSFET, because the GaN HEMT’s drift resistance dominates at such high voltage. At lower voltages, the GaN device resistance drops rapidly with VBR, so the MOSFET contribution becomes increasingly significant. For this reason, cascode solutions are practical and attractive for higher voltages (above roughly 200 V), whereas for 100–150 V class devices, monolithic e-mode GaN is generally preferable.
The direct-drive (enable) variant exposes the depletion-mode GaN gate directly to the external driver (typically 0 V on, -12 to -14 V off). The silicon MOSFET serves as a safety “enable” switch, connected to the gate driver’s undervoltage lockout (UVLO). During normal operation, the silicon device remains on and experiences no switching; it only blocks the GaN gate if supply fails. This configuration offers precise control of GaN dynamics but requires bipolar drive capability.
Reverse conduction in HEMT transistors
Reverse conduction behavior is a clear advantage of enhancement-mode GaN HEMTs. The source potential increases in relation to the gate when current is forced from the source to drain while the device is nominally off.
This process continues until the threshold condition for the formation of 2DEG is reached beneath the gate region. The channel now reorganizes and conducts in the opposite direction. Unlike the body diode of a silicon MOSFET, which depends on minority-carrier injection and storage, this is a majority-carrier mechanism. So, there is no stored minority charge and consequently no reverse-recovery penalty.
A positive gate voltage establishes the 2DEG channel during forward conduction, enabling current to move from the drain to the source. When reverse conduction occurs, as it does during a synchronous rectifier’s dead time, current moves from the source to the drain when the drain is at least the threshold voltage lower than the gate.
Conduction is then determined by channel resistance, and the device functions similarly to a low-drop diode. In contrast to silicon MOSFETs, which suffer reverse-recovery losses because of charge storage effects, current almost immediately stops once the reverse bias is eliminated.
Vertical GaN and substrate choices
Instead of using lateral 2DEG transport, vertical GaN transistors employ a conduction path perpendicular to the wafer surface. In a typical structure, p-GaN regions linked to the source extend from the surface toward the drain, and the drain contact is positioned at the bottom of a thick n-GaN drift region. When a negative gate voltage is applied, the n-GaN between the p-regions beneath the gate is depleted, preventing current flow.
The depleted region collapses and electrons move vertically from source to drain when the gate is positively biased. This architecture has the potential to compete with high-voltage SiC devices because it can support breakdown voltages above 1000 V while maintaining quick switching. The sub-650 V market is dominated by lateral GaN, mainly because silicon substrates are more affordable and scalable.
The cost of standard 200-mm silicon wafers is only a few tens of dollars per wafer, which enables direct reuse of established CMOS fabs and high-volume manufacturing, including the potential for monolithic integration of sensing circuits and drivers. Bulk GaN substrates for vertical devices, on the other hand, are still restricted to small diameters (usually ≤150 mm) and cost several hundred to over a thousand dollars per wafer, or tens of dollars per cm². This severely limits cost competitiveness at mid voltages.
From a performance perspective, lateral GaN HEMTs benefit from the creation of a high-density 2DEG, which offers exceptionally high electron mobility and low channel resistance. This translates into excellent light-load efficiency and high-frequency operation, which are essential for applications like DC-DC converters, server power supplies, telecom, and consumer fast chargers.
Vertical architectures, currently dominated by SiC MOSFETs, continue to be the preferred solution for voltages above ~900 V because they provide superior robustness at high electric fields and decouple blocking voltage from lateral device dimensions. While SiC and future vertical GaN aim for high-voltage applications, lateral GaN emphasizes cost-performance optimization over voltage scaling in this regime, solidifying its leadership in the mid-voltage range.
Building a GaN HEMT transistor
Fabrication of a GaN HEMT begins with epitaxial growth of the GaN/AlGaN heterostructure on a foreign substrate. Unlike silicon devices, where the active layer matches the substrate, GaN HEMTs require heteroepitaxy, growing a wurtzite crystal on a substrate with mismatched lattice constant and thermal expansion.
Four substrate materials dominate: bulk GaN, sapphire (Al₂O₃), silicon carbide (SiC), and silicon (Si). Each offers trade-offs in lattice mismatch, thermal expansion coefficient, thermal conductivity, and cost. Silicon (111) orientation substrates have emerged as the commercial workhorse due to their low cost ($1–2 per 200 mm wafer) and compatibility with existing CMOS fabrication infrastructure, despite a 17% lattice mismatch (a_GaN = 3.189 Å vs. a_Si = 3.84 Å) and thermal expansion difference of 3 × 10⁻⁶ K⁻¹.
Heteroepitaxy grows one crystal on a dissimilar substrate. Metal-organic chemical vapor deposition (MOCVD) deposits the GaN/AlGaN layers. The process starts with an AlN seed layer on the substrate to initiate nucleation. An AlGaN buffer layer creates the transition to pure GaN crystal structure. A thick GaN layer forms the semi-insulating base. Finally, a thin AlGaN barrier layer induces strain that forms the 2DEG conduction channel.
Figure 3 illustrates the complete epitaxial stack from substrate to 2DEG interface. For enhancement-mode devices, a p-GaN cap layer grows atop the AlGaN barrier, introducing positive charge to deplete the 2DEG at zero gate bias (Figure 4). This stack enables lateral electron transport parallel to the surface, distinguishing GaN HEMTs from vertical silicon MOSFETs.
Figure 3 The illustration highlights basic steps involved in creating a GaN heteroepitaxial structure: Starting silicon substrate (a), aluminum nitride (AlN) seed layer grown (b), various Al GaN layers grown to transition the lattice from AlN to GaN (c), GaN layer grown (d), and AlGaN barrier layer grown (e). Source: Efficient Power Conversion (EPC)
Figure 4 An additional GaN layer, doped with p-type impurities, can be added to the heteroepitaxy process when producing an enhancement-mode device. Source: Efficient Power Conversion (EPC)
Ohmic contacts and metallization
Source and drain electrodes must form low-resistance ohmic contacts to the 2DEG, penetrating the AlGaN barrier. Multiple metal layers and high-temperature annealing create reliable shunts. The gate electrode sits atop the AlGaN (or p-GaN), modulating the channel via electric field.
Back-end processing adds multilevel copper interconnects with tungsten vias, scaling gate width across thousands of parallel cells. Final passivation (SiNₓ) protects the surface and shapes electric fields to prevent premature breakdown.
Chip-scale packages (BGA and LGA) minimize parasitics, supporting megahertz switching with minimal ringing. Recent advances in QFN (Quad, Flad, No-Lead) have brought packaging alternatives that have minimal compromises in parasitic inductance, resistance, and thermal conductivity.
In either chip-scale of QFN packages, lateral conduction enables bottom-side cooling and ultra-low inductance packaging. Ball grid array (BGA) formats use SnAgCu micro-bumps (150 µm pitch) for 100–650 V devices (1.5 × 1.0 mm² footprint). LGA variants (3.9 × 2.6 mm²) handle 100 V half-bridges at 10 A continuous. Package loop inductance drops below 0.2 nH, supporting dI/dt >2000 A/µs without significant ringing—impossible in wire-bonded discrete packages
The path to monolithic integration
The lateral architecture of GaN HEMTs—where current flows parallel to the surface—eliminates the need for deep vertical vias or trenches, enabling unprecedented levels of monolithic integration. Unlike vertical silicon or SiC devices, multiple passive and signal-level transistors and passive components occupy the same epitaxial plane, with interconnects formed in overlying metal layers. This allows fabrication of complete power stages on a single die smaller than a grain of rice.
Figure 5 A typical process creates solder bars on an enhancement-mode GaN HEMT (not to scale). Source: Efficient Power Conversion (EPC)
Monolithic GaN stages eliminate interconnect parasitics that plague discrete implementations:
- No bond wires: Package inductance <0.2 nH vs. 1–5 nH with discrete multi-chip QFN
- Zero common source and gate loop inductance
- Pin count reduction: 99% fewer external connections vs. discrete half-bridge + drivers
Compared to silicon DrMOS (driver + MOSFET), GaN integration yields:
- 10× lower QG → MHz switching without excessive gate losses
- Zero QRR → no reverse recovery in synchronous rectification
- 25× smaller die area → lower cost at equivalent performance
Maurizio Di Paolo Emilio is director of global marketing communications at Efficient Power Conversion (EPC), where he manages worldwide initiatives to showcase the company’s GaN innovations. He is a prolific technical author of books on GaN, SiC, energy harvesting and data acquisition and control systems, and has extensive experience as editor of technical publications for power electronics, wide bandgap semiconductors, and embedded systems.
Editor’s Note:
The content in this article uses references and technical data from the book GaN Power Devices for Efficient Power Conversion (Fourth Edition) authored by Alex Lidow, Michael de Rooij, John Glaser, Alejandro Pozo Arribas, Shengke Zhang, Marco Palma, David Reusch, Johan Strydom.
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