AI training clusters, smart factory vision systems and SmartNIC-based networking platforms share a common architectural shift: multiple heterogeneous chips working together. Modern systems routinely combine FPGAs, ASICs, GPUs and CPUs, each with different frequencies and performance needs. Traditionally, engineers assigned a dedicated timing device to each of these chips. This increases system size and power consumption while it limits overall performance and cohesion. While clock generators have emerged to address these needs, maintaining precise synchronization across increasingly faster and more complex heterogeneous systems is a growing design challenge.
Enter the SiTime Chorus™ 2, a wide-frequency-range programmable clock generator. Building on the success of the Chorus family, the Chorus 2 clock generator drives superior performance through a rich feature set compared to competitive solutions. Chorus 2 clock generators deliver up to 2x better performance, 2x lower jitter and up to 2.5x less output skew and greater spread spectrum clock support. It has the maximum frequency planning flexibility, delivering design ease along with dynamic, precise signal synchronization and optimized system power.
The Chorus 2 clock generator addresses AI and high performance computing (HPC) timing challenges in data center platforms, mid-tier networking equipment and a broad range of industrial and high-end consumer applications.
More Outputs and Programmable Flexibility to Scale Up and Down
Chorus 2 replaces up to 8 or 12 discrete oscillators or clock signals with a single device. With up to 20 flexible configurations, each output can operate at a different frequency or meet distinct conditions. Unused outputs can be disabled to save power and reduce noise, making the device adaptable to a wide range of applications.
The Chorus 2 device proves especially valuable when designs require high performance networking clocks or PCIe Gen1–7 support. In complex systems such as datacenter servers, GPU baseboards often demand multiple PCIe and SerDes clocks to supply PCIe switches or re-timer ASICs. With 8 or 12 outputs, Chorus 2 consolidates these diverse timing requirements, simplifying design while ensuring precise and reliable performance across all components. In addition, Chorus 2 clock generators are pin-to-pin compatible with other market-solutions. In these cases, this more flexible, high performance device can be a direct a replacement in existing designs.
Chorus 2 Clock Generator Key Features
- Latest PCI Express (PCIe) clock compliance: PCIe Gen7 compliant
- Superior SerDes jitter performance:1.3x to 2x better jitter performance (
- Maximum output Mux configuration flexibility: Ultra-low-noise coupling Mux design supports flexible output configurations — Any frequency clock by fractional divider
- Individual spread spectrum clocks: Four independent spread spectrum clocks
- Precise output-to-output skew control: 1.6X~2.5X lower skew variations
- Multiple device configurations supported: Up to 20 custom-configurations, one-time programmable (OTP).
Precision Timing for Advanced Systems Across Industries
In today’s electronic systems, timing has evolved to become a central design consideration. The Chorus 2 clock generators make that transition seamless. By coordinating sequencing across components and ensuring signal integrity, Chorus 2 simplifies system architecture while boosting performance. Designers gain the benefits of fewer components, lower power consumption and reduced board space, while tighter integration delivers more efficient and scalable systems. What once required a collection of discrete functions is now converging into a unified foundation of precision and control — delivering the performance, functionality and flexibility needed to power the next generation of electronic systems.
For more information, check out the Chorus 2 clock generator. Product is in volume production. Samples available immediately: SiT95272 (12 outputs at 6 mm x 6 mm 48 pin quad flat no-lead, QFN, package), SiT95278 (8 outputs at 5 mm x 5 mm 40 pin QFN package).