CoWoS, wafer-scale and CoWoP: Why AI packaging bottleneck is moving

Advanced AI systems are forcing the semiconductor industry to rethink the boundary between silicon, package, board, power delivery, memory, cooling, and manufacturing. For several years, the dominant discussion has centered on advanced packaging capacity, high-bandwidth memory (HBM) integration, large interposers, organic substrate constraints, glass-core substrates, and scaling limits of 2.5D and 3D integration.

That discussion remains valid. But a deeper system question is emerging. What happens if the package substrate is no longer the center of the system-integration hierarchy? This question becomes especially important when comparing three architectural directions:

CoWoS-style 2.5D integration
Wafer-scale integration
CoWoP/chip-on-wafer-on-platform-PCB concepts

Each approach is trying to solve the same industry problem: how to scale AI compute density, memory bandwidth, transient power delivery, thermal control, and multi-die integration beyond the physical limits of conventional packaging stacks. However, each architecture moves the bottleneck to a different place.

Chip-on-Wafer-on-Substrate (CoWoS) makes advanced packaging central to AI and high-performance compute (HPC) scaling. Next, wafer-scale integration pushes silicon integration to the extreme. Finally, Chip-on-Wafer-on-PCB (CoWoP) may create a new middle architecture where the platform PCB becomes part of the governed realization corridor.

Therefore, it’s not only a packaging phenomenon; it’s also about system realization.

CoWoS: The proven advanced packaging path

CoWoS has become one of the most important advanced-packaging architectures for AI accelerators and HPC silicon. It enables logic die, HBM stacks, and high-density interconnect to be integrated through an interposer and then connected to a package substrate and board.

The strength of CoWoS is apparent. It provides high-density die-to-die and die-to-HBM connectivity, supports large AI/HPC modules, and has become a production-proven integration path for high-bandwidth systems. However, CoWoS also exposes the limits of the modern package stack. See the complex corridor below:

Die/HBM → interposer → package substrate → PCB → voltage regulator module (VRM)/system

The package substrate must support escape routing, power delivery network (PDN) distribution, coefficient of thermal expansion (CTE) transition, mechanical stability, manufacturing yield, decoupling strategy, signal integrity (SI)/power integrity (PI) control, warpage management, and board attach reliability. And as package size increases, these challenges become more critical.

Many of the hardest problems in advanced AI packaging aren’t located in silicon; they occur in the package and package-to-board realization path.

Warpage
Substrate availability
Package size
Thermal gradients
PDN impedance
Loop inductance
dI/dt response
Decoupling placement
SI/PI discontinuities
Manufacturing complexity

In other words, CoWoS is powerful, but the package substrate becomes a major convergence burden. This is why glass-core substrates are receiving so much attention.

Glass substrates help, but they don’t remove corridor

Glass can improve dimensional stability, reduce warpage, provide better CTE control, support finer routing environments, and improve vertical power-delivery paths with through-glass vias (TGVs). For large AI/HPC packages and future electro-optical integration, these advantages are meaningful.

But glass should not be treated as a complete escape from package realization complexity. In most practical glass-core substrate architectures, the glass is primarily the core and the build-up layers still there. That means many high-speed routing-density challenges remain concentrated in the top build-up structure.

Moreover, bottom-side routing through the core is still not equivalent to short top-side interconnect. Signals passing through TGVs and returning through lower layers still face discontinuities, parasitics, reference-plane challenges, and SI/PI governance requirements.

So, glass changes the package problem, but it does not eliminate it. This distinction matters because CoWoP is not simply about replacing one substrate material with another. It’s about asking whether the realization hierarchy itself can change.

Wafer-scale integration: The extreme silicon path

Wafer-scale integration takes a different route. Instead of assembling many dies through a package-level integration strategy, it expands the silicon system itself. The result is an extremely large compute fabric with direct wafer-level integration, specialized power delivery, cooling, redundancy, and system infrastructure.

This can be technically powerful because it removes many conventional package boundaries and creates a very large on-wafer compute fabric. At the same time, however, wafer-scale integration does not eliminate realization complexity. It relocates it.

The board, power architecture, cooling system, mechanical structure, redundancy strategy, yield-management approach, and system-level service model must all adapt around a very large silicon platform. A useful way to summarize the difference is that wafer-scale integration expands silicon until the system must adapt around it. That can be attractive for certain AI workloads and specialized systems, but it’s not necessarily the most flexible path for every AI accelerator, custom ASIC, chiplet platform, or memory-rich architecture.

CoWoP: A possible middle architecture

CoWoP is interesting because it may offer a third path. Instead of the traditional path comprising die/HBM, interposer, package substrate and PCB, CoWoP points toward a shorter realization path.

Die/HBM → interposer/wafer-level structure → platform PCB

The deeper architectural value is not simply cost reduction. The deeper value is that CoWoP may change the power, memory, mechanical, and system-realization architecture. If the package substrate is reduced or removed, the system no longer needs to carry as much of the convergence burden through three separate layers: interposer, package substrate, and PCB.

Instead, the corridor becomes more direct. However, this directness should not be oversimplified. A realistic CoWoP architecture cannot simply assume that a fine-pitch silicon interposer can land directly onto a platform or PCB without a transition strategy.

The most important challenge may be the transition between wafer/interposer precision and PCB manufacturability. That transition may define whether CoWoP becomes a practical system architecture or remains only an attractive concept.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 1 of the mini-series on advanced packaging. Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, UCIe routing, and trusted realization governance.

Source link