Beyond low-power design and beyond multi-threshold-voltage libraries, clock and power gating, and voltage-frequency scaling lies the strange land of ultra-low-power systems. Here, power comes from tiny, semi-permanent batteries or energy scavenging, and it comes in microwatts or nanowatts, not milliwatts.
For system-on-chip (SoC) designers, this is the alien realm of ultra-low voltage (ULV): supply voltages near or below transistor threshold voltages. In this realm, many things are unfamiliar to conventional SoC designers. Foundational IP must be different. Familiar-looking tool flows may hide important differences in tools and skills. New challenges appear—threats that could sink a project.
ULV design explored
All differences in ULV design begin with the definition: ULV circuits use a VDD near or below the threshold voltage of the process’s MOSFETs. This leads to several important effects.
First, of course, is energy savings, the whole reason for ULV design. ULV works because instantaneous power is quadratic in supply voltage. So, the instantaneous power consumed when a circuit is active, and hence the energy required to complete a task, can be significantly lower at lower VDD.
Usually, designers will talk not about power consumption, but about the energy required to complete an operation, typically in nanoJoules. This is a preferred metric because, in ultra-low-power systems, ULV SoCs are usually quiescent for long periods, wake to perform specific tasks, and then reenter their trance. This activity pattern makes peak and average power figures poor indicators of energy consumption and, therefore, battery life or drain on energy scavengers.
But this energy benefit comes with challenges. Near threshold voltage, a MOSFET gate exerts only weak control over channel current. Leakage can be high, and the difference between ION and IOFF is small.
Maintaining the separation—the values of 1 and 0—throughout each net’s stages and across clock trees becomes a fundamental undertaking for the design team. The separation is already low, and other factors conspire against it. Interconnect parasitics, noise, and process variations can prevent circuits from working reliably. So, ULV design requires special measures.
Foundational IP
One of the first challenges designers will face is that conventional low-power libraries will not work for most ULV designs. Cells in standard libraries may be optimized for performance or packing density, but not for operation at ultra-low voltages. Some cells in the library are likely to fail or become unreliable simply because they cannot maintain the distinction between 1 and 0, even under ideal conditions. Add in parasitics, noise, and variations, and the library cells cannot cope. New, custom cell designs are needed.
In addition, some cells, such as high-fan-in gates, may work correctly but impose so much delay that they become useless. Such cells need to be eliminated from libraries. Other cells—ULV-level shifters, in particular—must be designed for the specific voltage range the design requires.
SRAM is another problem. The standard 6T SRAM cell usually cannot perform reliable reads and writes at ULV. Adding custom assist circuitry can help, as can simply enlarging the bit cell. The dual-rail design will work better (Figure 1). And some designers avoid the issue by making the SRAM a high-voltage island surrounded by level shifters, sacrificing energy efficiency for simplicity.
Figure 1 The dual-rail SRAM design highlights array on HV, periphery on ULV, and level shifter on the WL path. Source: Faraday Technology
Fine-grained characterization
Cells that work at ULV are necessary, but far from sufficient. Traditional delay modeling at a few process corners is hopelessly inadequate to achieve timing closure in a ULV design. In this voltage region, delay can vary exponentially with voltage, often in a non-Gaussian distribution. A traditional approach using a few corners would result in hopelessly large design margins.
We have found that fine-grained characterization of the foundational libraries, using voltage increments no larger than 50 mV and often finer, is a minimum requirement. This data must be captured in an advanced format such as Liberty Variation Format with Moments (LVFM). This allows statistical timing tools—using knowledge of the intended supply voltage range of the finished system—to produce design margins that are not overly pessimistic.
So, use knowledge of the intended supply voltage range of the finished system to produce design margins that are not overly pessimistic (Figure 2).
Figure 2 This data must be captured in an advanced format such as LVFM. This lets statistical timing tools produce design margins that are not overly pessimistic. Source: Faraday Technology
The bottom line for design teams is that ULV SoC design requires custom ULV foundational libraries, characterized over the expected operating range with very fine granularity.
Tool flow
Fortunately, ULV SoC design can use standard modern synthesis and place-and-route tools compatible with the LVFM format (Figure 3). But the standard flow still requires additional ULV expertise. For example, the synthesis tool must support the custom ULV libraries.
Figure 3 Standard Tools must possess critical ULV expertise. Source: Faraday Technology
All tools must recognize that, at ULV, timing will be extremely sensitive to routing paths due to both parasitic impedance and noise. Static timing tools must be variation-aware and able to consume LVFM data to exploit the libraries’ fine-grained characterization and minimize design margins.
Special attention must also be given to noise: crosstalk, supply transients, and even substrate noise. This may come down to the designers’ skill in floorplanning and in guiding placement and routing tools to anticipate and avoid noise sources.
The concluding steps
The ULV SoC design requires additional work to reach signoff. But then, both silicon bring-up and manufacturing test also have special requirements at ULV. Test equipment needs high accuracy at low voltages and, of course, a low-noise floor. So, load boards must be designed with extra care about leakage and parasitics.
During both silicon evaluation and manufacturing test, pay special attention to the power-on reset sequence across the entire operating voltage range, as it’s particularly vulnerable in ULV designs. Also, carefully test those ULV-level shifters.
Finally, the OSAT organization or internal manufacturing test facility must use the advanced binning strategy. Because process variations—even across a wafer—are so significant at ULV, it’s necessary to perform accurate voltage-speed binning (Figure 4). This separates chips that meet the requirements across the intended operating voltage range from those that work only at higher voltages.
Figure 4 Accurate voltage binning separates chips that meet requirements across the intended operating range from those that work only at higher voltages. Source: Faraday Technology
Why ULV expertise matters
ULV design facilitates SoCs that can operate almost indefinitely on tiny batteries or scavenged power. Custom libraries, fine-grained characterization, advanced design tools, and ULV-experienced designers make these projects achievable. Moreover, deep foundry and OSAT relationships make volume production realistic.
Some large design groups have these resources, expertise, and relationships in-house and can confidently undertake ULV SoC designs independently. But in many cases, an organization will want to deploy its assets across the overall low-energy system rather than to the specialized needs of the SoC design. In these cases, a traditional SoC design team can partner with an organization with extensive ULV experience.
The right ULV expert must be ideally positioned to partner with a traditional SoC design team entering ULV land. The land is indeed strange and strewn with risks. But with the right partner, it’s the land through which the path to technical and commercial success lies.
C.H. Chien has dedicated 33 years to IC design; his industry experience includes IP development and IC design flow. He also has 10 years of experience managing overseas R&D teams. Chien worked as a director at MediaTek and GlobalFoundries before joining Faraday Technology Corp.
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