Power Tips #158: Using a programmable logic device as an LLC controller

Inductor-inductor-capacitor (LLC) applications that don’t require a closed control loop can benefit from simple and low-cost implementations.

High-power applications that require isolation and prioritize high efficiency often use inductor-inductor-capacitor (LLC) converters in either a half- or full-bridge configuration implemented on the primary side, depending on the voltages and power levels. Synchronous rectification is often mandatory to achieve good efficiency, especially with low output voltages.

When looking for closed-loop LLC controllers, there are various options on the market, which offer features for protection and a precise ±3% regulated output. For open-loop applications that can tolerate an unregulated output of ±10%, many closed-loop controller features aren’t necessary, and it often takes some effort to disable certain functions to get an open-loop design working.

LLC controller features

The feature set for an open-loop LLC controller can be divided into mandatory and optional features. Mandatory features include soft start, enable input, over-current protection (OCP) with cycle-by-cycle current limiting (hiccup mode or latch-off), and driving the primary-side power stage. Optional features may include power-good output, over- and under-voltage lockout, and driving the synchronous rectifiers.

The Texas Instruments programmable logic device (TPLD) family can implement these features to achieve a cost-effective solution for open-loop applications. Figure 1 is a block diagram of the TPLD2001-Q1. This device includes various logic blocks, internal oscillators with a clock frequency up to 25MHz, a state machine, and analog comparators, making it a good match for the features that an open-loop LLC controller requires.

Figure 1 This block diagram shows the building blocks available in the TPLD2001-Q1. Source: Texas Instruments

Open-loop LLC implementation

Generating control signals for the power stages is a simple task. For low switching frequencies, designers can use the internal pulse-width modulation (PWM) generators, but higher frequencies require a logic-based approach. One possible implementation is a classical ring buffer built from configurable one-shot blocks, which generate two inverted signals for the primary side and add dead time. Figure 2 shows an implementation that generates the two control signals for the primary side as well as two control signals for driving the synchronous rectifiers on the secondary side, with adjustable dead bands between primary and secondary.

Figure 2 This example implementation generates four output signals with an adjustable dead band, all within a single TPLD2001-Q1. Source: Texas Instruments

In this way, there is no need for a specialized synchronous rectifier controller. To enable synchronous rectification, a comparator channel can measure the primary-side current to enable synchronous rectification as soon as the converter input current rises above a decision threshold.

Figure 3 shows a design example using synchronous rectification without a specialized controller. The use of LMG2104-Q1 integrated half bridges simplifies the TPLD implementation, since these devices take care of the required dead time for the primary side by themselves.

Figure 3 This overview of an example design uses TI’s TPLD2001-Q1 as a controller. Source: Texas Instruments

It is possible to achieve OCP using the internal comparators, which disable switching if the primary-side current gets too large. The amount of available logic gates enables an implementation that does cycle-by-cycle current limiting by skipping cycles if the primary-side current reaches a set limit (Figure 4). After a certain period of time, the control logic then enters hiccup mode or latch-off, which either one-shots or one of the TPLD’s counters can easily implement. Also, during soft start, the disabled synchronous rectification ensures that no unwanted current flows from the output back to the input of the converter.

Figure 4 This example current-limit implementation also fits within the TPLD2001-Q1. Source: Texas Instruments

An enable input completes the connectivity requirements and resets the device so that it goes through soft start when enabled. For devices with several analog inputs, it is easy to add under-voltage lockout and over-temperature protection features.

Of course, there are some limitations to these programmable logic devices, although many are easy to overcome. When using the internal PWM generators, the maximum frequency is limited to <100 kHz because of the fixed-period counter value.

Because the open-loop LLC topology requires no duty cycle or frequency variation, you can build your own control signal generator using the available logic cells within the TPLD2001-Q1 to achieve your desired output frequency. A 25 MHz clock frequency is high enough to generate suitable dead times and output signal frequencies up to about 500 kHz. Higher frequencies are possible; however, the dead time becomes an increasing percentage of the total switching cycle, thereby lowering efficiency.

When using synchronous rectifier controllers and integrated power stages – which take care of the dead time by themselves – this efficiency penalty is no longer an issue. Figure 5 shows the switching waveform of the design example, using a TPLD for controlling the primary side and synchronous rectification.

Figure 5 This graph from the design example shows the switch node and current waveform. Source: Texas Instruments

If you don’t need more than two analog inputs, a smaller device such as the TPLD1202-Q1 is an option. But since that device has only one comparator, the inputs are multiplexed and therefore too slow for OCP. The discrete analog comparators available within the TPLD2001-Q1 are fast enough to implement OCP and can be used for other features like the previously described simple synchronous rectification control. If OCP is the only analog feature that you require, the smaller TPLD1202-Q1 device variant may be a good fit for more cost-sensitive applications.

Conclusion

The TPLD family offers enough flexibility to implement relatively complex control mechanisms for power converters. LLC applications that don’t require a closed control loop can benefit from a simple and low-cost implementation. Although this power tip is based on a working solution, depending on the overall requirements (for example, bidirectional operation or higher switching frequencies), some device limitations could demand a different approach. Here, the TI MSPM0 microcontroller could become a valid option.

As part of the Power Design Services team, Björn Görner has eight years of experience designing custom power solutions and reference designs, with the main focus on automotive applications. He is a regular presenter for Power Supply Design Seminars, which Texas Instruments offers biannually to educate and support anyone interested in power conversion.

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